3.3 VOLT CMOS SyncFIFO
TM
WITH
BUS-MATCHING
256 x 36
IDT72V3623
1,024 x 36
IDT72V3643
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
•
•
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Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3643–1,024 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using
EF
and
FF)
or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
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Reset clears data and configures FIFO, Partial Reset clears
data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723623/723643
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Port-A
Control
Logic
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Bus-
Matching
Input
Register
Output
Register
FIFO1
Mail1,
Mail2,
Reset
Logic
36
36
RAM ARRAY
36
36
256 x 36
1,024 x 36
A
0
-A
35
Write
Pointer
Read
Pointer
B
0
-B
35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
10
Timing
Mode
Port-B
Control
Logic
Mail 2
Register
MBF2
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 2018
DSC-4662/8
1
©
2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The IDT72V3623/72V3643 are pin and functionally compatible
versions of the IDT723623/723643, designed to run off a 3.3V supply for
exceptionally low power consumption. These devices are monolithic,
high-speed, low-power, CMOS unidirectional Synchronous (clocked)
FIFO memory which supports clock frequencies up to 100 MHz and has
read access times as fast as 6.5 ns. The 256/1,024 x 36 dual-port SRAM
FIFO buffers data from Port A to Port B. FIFO data on Port B can output
in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian
configurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employs a synchronous interface. All data transfers through a port are gated
PIN CONFIGURATION
CSA
FF/IR
NC
PRS
V
CC
AF
NC
MBF2
MBA
RS1
FS0/SD
GND
GND
FS1/SEN
RS2
MBB
MBF1
V
CC
AE
NC
EF/OR
NC
GND
CSB
W/RB
ENB
INDEX
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
V
CC
V
CC
B35
B34
B33
B32
GND
GND
B31
B30
B29
B28
B27
B26
V
CC
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
V
CC
B15
B14
B13
B12
GND
B11
B10
NOTE:
1. NC – no internal connection
A9
A8
A7
A6
GND
A5
A4
A3
SPM
V
CC
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
V
CC
B7
B8
B9
4662 drw02
TQFP (PK128, order code: PF)
TOP VIEW
2
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
to the LOW-to-HIGH transition of a port clock by enable signals. The
clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFO via two
mailbox registers. The mailbox registers' width matches the selected Port
B bus width. Each mailbox register has a flag (MBF1 and
MBF2)
to signal
when new mail has been stored.
Two kinds of reset are available on these FIFOs: Reset and Partial Reset.
Reset initializes the read and write pointers to the first location of the memory array
and selects serial flag programming, parallel flag programming, or one of three
possible default flag offset settings, 8, 16 or 64.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings.
These devices have two modes of operation: In the
IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the
First Word Fall Through mode
(FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/FWFT pin during Reset
determines the mode in use.
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a
combined Full/Input Ready Flag (FF/IR). The
EF
and
FF
functions are selected
in the IDT Standard mode.
EF
indicates whether or not the FIFO memory is
empty.
FF
shows whether the memory is full or not. The IR and OR
functions are selected in the First Word Fall Through mode. IR indicates
whether or not the FIFO has available memory locations. OR shows
whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
The FIFO has a programmable Almost-Empty flag (AE) and a
programmable Almost-Full flag (AF).
AE
indicates when a selected
number of words remain in the FIFO memory.
AF
indicates when the
FIFO contains more than a selected number of words.
FF/IR
and
AF
are two-stage synchronized to the port clock that writes data
into its array.
EF/OR
and
AE
are two-stage synchronized to the port clock that
reads data from its array. Programmable offsets for
AE
and
AF
are loaded in
parallel using Port A or in serial via the SD input. The Serial Programming Mode
pin (SPM) makes this selection. Three default offset settings are also provided.
The
AE
threshold can be set at 8, 16 or 64 locations from the empty boundary
and the
AF
threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the Power Down state.
The IDT72V3623/72V3643 are characterized for operation from 0°C
to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using high speed, submicron CMOS
technology.
3
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
A0-A35
AE
AF
B0-B35
BE/FWFT
Name
Port A Data
Almost-Empty Flag
(Port B)
Almost-Full Flag
(Port A)
Port B Data
Big-Endian/
First Word
Fall Through
I/O
I/O
O
O
I/O
I
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of
words in the FIFO is less than or equal to the value in the Almost-Empty B offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian
operation. In this case, depending on the bus size, the most significant byte or word written to
Port A is read from Port B first. A LOW on BE will select Little-Endian operation. In this case,
the least significant byte or word written to Port A is read from Port B first. After Master Reset,
this pin selects the timing mode. A HIGH on
FWFT
selects IDT Standard mode, a LOW
selects First Word Fall Through mode. Once the timing mode has been selected, the level
on
FWFT
must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size
and endian arrangement for Port B. The level of BM must be static throughout device
operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB.
FF/IR
and
AF
are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA.
EF/OR
and
AE
are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A.
The A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on
Port B. The B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
This is a dual function pin. In the IDT Standard mode, the
EF
function is selected.
EF
indicates
whether or not the FIFO memory is empty. In the FWFT mode, the OR function is selected.
OR indicates the presence of valid data on the B0-B35 outputs, available for reading.
EF/OR
is
synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
This is a dual function pin. In the IDT Standard mode, the
FF
function is selected.
FF
indicates
whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
FF/IR
is
synchronized to the LOW-to-HIGH transition of CLKA.
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming.
During Reset, FS1/SEN and FS0/SD, together with
SPM,
select the flag offset programming
method. Three offset register programming methods are available: automatically load one of
three preset values (8, 16, or 64), parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an
enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a
rising edge on CLKA load the bit present on FS0/SD into the X and Y registers. The number
of bit writes required to program the offset registers is 16 for the IDT72V3623 and 20 for the
IDT72V3643. The first bit write stores the Y-register MSB and the last bit write stores the
X-register LSB.
BM
Bus-Match Select
(Port B)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
CSB
EF/OR
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Full/Input
Ready Flag
(Port A)
Flag Offset
Select 1/
Serial Enable
Flag Offset
Serial Data
I
I
O
ENA
ENB
FF/IR
I
I
O
FS1/SEN
FS0/SD
I
4
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
MBA
MBB
Name
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register Flag
I/O
I
I
Description
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1
register for output and a LOW level selects FIFO data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
register. Writes to the mail1 register are inhibited while
MBF1
is LOW.
MBF1
is set HIGH by
a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1
is set HIGH following either a Reset (RS1) or Partial Reset (PRS).
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-
to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2
is set
HIGH following either a Reset (RS2) or Partial Reset (PRS).
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory
and sets the Port B output register to all zeroes. A LOW-to-HIGH transition on
RS1
selects the
programming method (serial or parallel) and one of three programmable flag default offsets.
It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions
of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
RS1
is LOW.
A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and
sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size,
endian arrangement, programming method (serial or parallel), and programmable flag settings
are all retained.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus
size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects
parallel programming or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB
is LOW.
MBF1
O
MBF2
Mail2 Register Flag
O
RS1, RS2
Resets
I
PRS
Partial Reset
I
SIZE
Bus Size Select
(Port B)
Serial Programming
Mode
Port A Write/
Read Select
Port B Write/
Read Select
I
SPM
W/RA
W/RB
I
I
I
5
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