INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4030B
gates
Quadruple exclusive-OR gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple exclusive-OR gate
DESCRIPTION
The HEF4030B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
HEF4030B
gates
Fig.2 Pinning diagram.
HEF4030BP(N):
HEF4030BD(F):
HEF4030BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.2 Logic diagram (one gate).
TRUTH TABLE
I
1
L
H
L
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
I
2
L
L
H
H
O
1
L
H
H
L
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Quadruple exclusive-OR gate
HEF4030B
gates
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
Output transition times
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PLH
t
PHL
85
35
30
75
30
25
60
30
20
60
30
20
175
75
55
150
65
50
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
57 ns
+
(0,55 ns/pF) C
L
24 ns
+
(0,23 ns/pF) C
L
22 ns
+
(0,16 ns/pF) C
L
47 ns
+
(0,55 ns/pF) C
L
19 ns
+
(0,23 ns/pF) C
L
17 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
1 100 f
i
+ ∑(f
o
CL)
×
V
DD2
4 900 f
i
+ ∑(f
o
CL)
×
V
DD2
14 400 f
i
+ ∑(f
o
CL)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
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