Si5018
SiPHY™ OC-48/STM-16 C
LOCK AND
D
ATA
R
ECOVERY
IC W
ITH
FEC
Features
Complete high-speed, low-power, CDR solution includes the following:
Supports OC-48 /STM-16 & FEC
Low power—270 mW
(typ OC-48)
Small footprint: 4x4 mm
DSPLL™ Eliminates external
loop filter components
3.3 V tolerant control inputs
Exceeds all SONET/SDH jitter
specifications
Jitter generation
3.0 mUI
rms
(typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V Supply
Ordering Information:
See page 17.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Board level serial links
Pin Assignments
Si5018
CLKOUT+
CLKOUT–
15
GND
GND
Description
The Si5018 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/STM-16 data
rates. In addition, support for 2.7 Gbps data streams is also provided for
applications that employ forward error correction (FEC). DSPLL™
technology eliminates sensitive noise entry points thus making the PLL
less susceptible to board-level interaction and helping to ensure optimal
jitter performance.
The Si5018 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
REXT
VDD
GND
REFCLK+
REFCLK–
1
2
3
4
5
20 19 18 17 16
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
GND
GND
Pad
Connection
14
13
12
11
6
LOL
7
VDD
8
GND
9
DIN+
10
DIN–
Functional Block Diagram
LOL
D IN +
D IN –
2
BU F
D SPLL
TM
Phas e-Locked
Loop
R etim er
BU F
2
D OU T +
D OU T –
PW R D N /C AL
Bias
2
BU F
2
C LKOU T +
C LKOU T –
R EXT
R EF C LKIN +
R EF C LKIN –
Rev. 1.3 6/08
Copyright © 2008 by Silicon Laboratories
Si5018
Si5018
T
ABLE
Section
OF
C
ONTENTS
Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.3
3
Si5018
1. Detailed Block Diagram
Retim e
DOUT+
DOUT–
c
DIN+
DIN–
Phase
Detector
A/D
DSP
n
VCO
CLK
Divider
CLKOUT+
c
CLKOUT–
REFCLK+
REFCLK–
Lock
Detector
LOL
REXT
Bias
G eneration
Calibration
PWRDN/CAL
4
Rev. 1.3
Si5018
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5018 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5018 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "Typical Application Schematic‚" on page 9.
V
SIGNAL+
V
ICM
,V
OCM
Differential
I/Os
SIGNAL–
V
IS
Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
ID
,V
OD
(V
ID
= 2V
IS
)
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
C-D
DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
DOUT,
CLKOUT
t
F
t
R
80%
20%
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.3
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
