MIC59P50
Micrel
MIC59P50
8-Bit Parallel-Input Protected Latched Driver
General Description
The MIC59P50 parallel-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, and OUTPUT ENABLE func-
tions. Similar to the MIC5801, additional protection circuitry
supplied on this device includes thermal shutdown, under
voltage lockout (UVLO), and over-current shutdown.
The bipolar/MOS combination provides an extremely low-
power latch with maximum interface flexibility. The MIC59P50
has open-collector outputs capable of sinking 500mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V above V
EE
(50V sustaining). The drivers can be operated with a split
supply, where the negative supply is down to –20V and may
be paralleled for higher load current capability.
With a 5V logic supply, the MIC59P50 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors.
Each of these eight outputs has an independent over-current
shutdown at 500 mA. Upon current shutdown, the affected
channel will turn OFF and the flag will go low until V
DD
is
cycled or the ENABLE/RESET pin is pulsed high. Current
pulses less than 2µs will not activate over-current shutdown.
Temperatures above 165°C will shut down the device and
activate the open collector FLAG output at pin 1. The UVLO
circuit disables the outputs at low V
DD
; hysteresis of 0.5V is
provided.
Features
•
•
•
•
•
•
•
•
•
•
•
4.4 MHz Minimum Data Input Rate
High-Voltage, High-Current Outputs
Per-Output Over-Current Shutdown (500mA Typical)
Undervoltage Lockout
Thermal Shutdown
Output Fault Flag
Output Transient Protection Diodes
CMOS, PMOS, NMOS, and TTL Compatible Inputs
Internal Pull-Down Resistors
Low-Power CMOS Latches
Single or Split Supply Operation
Ordering Information
Part Number
MIC59P50BN
MIC59P50BV
MIC59P50BWM
* 300-mil “skinny DIP”
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
24-Pin Plastic DIP*
28-Pin PLCC
24-Pin Wide SOIC
Functional Diagram
STROBE
V DD
CLEAR FLAG ENABLE/RESET
Pin Configuration
(DIP and SOIC)
ISHUTDOWN
–
+
IREF
IOUT / N
FLAG
CLEAR
STROBE
1
2
3
4
5
6
THERMAL
SHUTDOWN
ILIMIT
24 VSS
23 OUTPUT
ENABLE/RESET
22 VDD
21 OUT 1
20 OUT 2
19 OUT 3
2.2R
+
–
UVLO
THERMAL
SHUTDOWN
S
R
Q
OUTPUT
COMMON
1.25V
R
IN 1
IN 2
IN 3
LATCHES
IN
IN 4
R1
70k
7
8
9
18 OUT 4
17 OUT 5
16 OUT 6
15 OUT 7
14 OUT 8
UVLO
13 COMMON
IN 5
R2
3k
Circuitry below dashed line is
included in each of the 8 channels.
V EE
IN 6
IN 7 10
IN 8 11
VEE 12
7-58
October 1998
MIC59P50
Micrel
Absolute Maximum Ratings
T
A
= +25°C
Output Voltage (V
CE
) .................................................... 80V
Supply Voltage (V
DD
) .................................................... 15V
(V
DD
– V
EE
) ............................................................... 25V
Input Voltage (V
IN
) ............................... –0.3V to V
DD
+0.3V
Continuous Collector Current (I
C
) ............................ 500mA
Protected Current ............................................ 1.5A,
Note 1
Power Dissipation (P
D
)
Plastic DIP (N) ......................................................... 2.4W
Derate above T
A
= +25°C ............................24mW/°C
PLCC (V) ................................................................. 1.6W
Derate above T
A
= +25°C ............................16mW/°C
Wide SOIC (WM) .................................................... 1.4W
Derate above T
A
= +25°C ............................14mW/°C
Operating Temperature (T
A
)
Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Junction Temperature (T
J
) ...................................... +150°C
ESD .........................................................................
Note 2
Note 1:
Note 2:
Each channel. V
EE
connection must be designed to minimize
inductance and resistance.
Devices are input-static protected but can be damage by
extremely high static charges.
PLCC Pin Configuration
OE/RESET
27
STROBE
CLEAR
FLAG
4
3
2
1
28
VDD
26
25
24
23
VEE
VSS
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
5
6
7
8
9
10
11
12
13
14
15
16
17
18
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
MIC59P50BV
22
21
20
19
COMMON
Allowable Output Current
ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C
MIC59P50BN
450
400
350
300
250
200
150
100
0
NUMBER OF OUTPUTS
CONDUCTING
SIMULTANEOUSLY
10
20
30
40
50
60
70
80
90
100
6
7
8
4
5
3
1 or 2
Typical Input
V DD
OUT 8
NC
IN 8
NC
VEE
NC
IN
7
PERCENT DUTY CYCLE
Pin Description
Pin
1
Name
FLAG
Description
Error Flag. Open Collector Output is Low upon Overcurrent Fault or
Overtemperature Fault. OUTPUT ENABLE/RESET must be pulled high to
reset the flag and fault condition.
Sets All Latches OFF (open).
Input Strobe Pin. Loads output latches when High.
Parallel Inputs, 1 through 8
Output Ground (Substrate). Most negative voltage in the system connects
here.
Transient suppression diodes cathode common pin.
Parallel Outputs, 8 through 1.
Logic Positive Supply voltage.
Output Enable Reset. When Low, Outputs are active. When High, outputs
are inactive and the Flag and outputs are reset from a fault condition. An
undervoltage condition emulates a high OE input.
Logic reference (Ground) pin.
2
3
4–11
12
13
14–21
22
23
CLEAR
STROBE
INPUT
V
EE
COMMON
OUTPUT
V
DD
OUTPUT ENABLE RESET
24
V
SS
October 1998
7-59
MIC59P50
Micrel
Electrical Characteristics
V
DD
= 5V; T
A
= +25°C; unless noted.
Limits
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Input Voltage
V
IN(0)
V
IN(1)
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
Note 3
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
V
OL
= 0.4V
V
OH
= 12.0V
V
DD
= 12V, Outputs Open
V
DD
= 10V, Outputs Open
V
DD
= 5.0V, Outputs Open
V
DD
= 12V, Outputs Open
V
DD
= 10V, Outputs Open
V
DD
= 5.0V, Outputs Open
V
DD
= 12V, Outputs Open, Inputs = 0V
V
DD
= 5.0V, Outputs Open, Inputs = 0V
V
R
= 80V, T
A
= +25°C
V
R
= 80V, T
A
= +70°C
Each Output
Note 4
3.5
3.0
I
F
= 350 mA
500
4.0
3.5
1.7
165
10
4.5
4.0
2.0
10.5
8.5
3.5
50
50
50
200
300
600
15
50
3.3
3.1
2.4
6.4
6.0
4.7
3.0
2.2
4.5
4.5
3.6
10.0
9.0
7.5
4.5
3.6
50
100
kΩ
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
CE
= 80V, T
A
= +25°C
V
CE
= 80V, T
A
= +70°C
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
0.9
1.1
1.3
Min.
Typ.
Max.
50
100
1.1
1.3
1.6
1.0
V
Units
µA
V
Input Resistance
R
IN
Flag Output Current
Flag Output Leakage
Supply Current
I
OL
I
OH
I
DD(ON)
(One output
active)
I
DD(ON)
(All outputs
active)
I
DD(OFF)
(Total)
mA
nA
mA
mA
mA
µA
mA
V
V
V
°C
Clamp Diode
Leakage Current
Over-Current Threshold
Start-Up Voltage
Minimum Operating V
DD
Clamp Diode Forward Voltage
Thermal Shutdown
Thermal Shutdown Hysteresis
NOTE 3:
NOTE 4:
I
R
I
LIM
V
SU
V
DD MIN
V
F
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic “1”.
Undervoltage lockout is guaranteed to release device at no more than 4.5V and disable the device at no less than 3.0V input logic voltage.
Truth Table
Output
IN
N
0
1
X
X
X
X
Strobe
1
1
X
X
0
0
Clear
0
0
1
X
0
0
Enable
0
0
X
1
0
0
X
X
X
X
ON
OFF
OUT
N
t–1
t
OFF
ON
OFF
OFF
ON
OFF
Information present at an input is transferred to its latch when
the STROBE is high. A high CLEAR input will set all latches
to the output OFF condition regardless of the data or STROBE
input levels. A high OUTPUT ENABLE will set all outputs to
the off condition, regardless of any other input conditions.
When the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches. If current shutdown is
activated, the OUTPUT ENABLE must be pulsed high to
restore operation and reset the Flag. Over temperature
faults are not latched and require no reset pulse.
X = Irrelevant
t–1 = previous output state
t = present output state
7-60
October 1998
MIC59P50
Micrel
CLEAR
F
STROBE
OUTPUT
ENABLE
A
C
B
C
B
A
C
B
G
IN N
D
OUT N
E
E
G
Timing Conditions
(T
A
A.
B.
C.
D.
E.
F.
G.
= +25°C, Logic Levels are V
DD
and V
SS
, V
DD
= 5V).
Minimum data active time before strobe enabled (data set-up time) ...................................................................... 50 ns
Minimum data active time after strobe disabled (data hold time) ............................................................................ 50 ns
Minimum strobe pulse width .................................................................................................................................. 125 ns
Typical time between strobe activation and output on to off transition .................................................................. 500 ns
Typical time between strobe activation and output off to on transition .................................................................. 500 ns
Minimum clear pulse width .................................................................................................................................... 300 ns
Minimum data pulse width ..................................................................................................................................... 225 ns
Typical Characteristic Curves
CURRENT SHUTDOWN DELAY (µs)
SATURATION VOLTAGE (V)
SUPPLY CURRENT (mA)
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
Output Saturation
Voltage vs. Temperature
I
L
= 350mA
6
5
4
Supply Current
vs. Temperature
7
6
5
4
3
2
1
Current Shutdown
Delay vs. Output Current
7
ALL OUTPUTS ON
V
DD
= 5V
V
DD
= 5V to 12V
3
2
1
0
–50
0
50
100
TEMPERATURE (°C)
150
ALL OUTPUTS OFF
V
DD
= 5V
V
DD
= 12V
0.5
0.6
0.7
0.8
OUTPUT CURRENT (A)
0.9
I
L
= 100mA
0.6
–50
0
50
100
TEMPERATURE (°C)
150
0
0.4
Current Shutdown
Threshold vs. Temperature
0.60
8
SUPPLY CURRENT (mA)
Supply Current
vs. Temperature
OUTPUT DELAY (ns)
260
240
Output Enable Delay
vs. Supply Voltage
R
L
= 50Ω
SHUTDOWN THRESHOLD (A)
7
6
5
4
3
2
1
0
–50
0
50
100
TEMPERATURE (°C)
150
ALL OUTPUTS OFF
V
DD
= 12V
ALL OUTPUTS ON
0.55
V
DD
= 5V
0.50
0.45
0.40
0.35
–50
V
DD
= 12V
220
200
180
160
140
120
100
5 6 7 8 9 10 11 12 13 14 15
SUPPLY VOLTAGE (V)
T
D
ON
T
D
OFF
0
50
100
TEMPERATURE (°C)
150
October 1998
7-61
MIC59P50
Micrel
Typical Applications
MIC59P50 Protected Relay Driver
10kΩ
+5V
FLAG
OUTPUT
1
2
STROBE
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
INPUT 8
3
4
5
6
LATCHES
ILIMIT
24
THERMAL
SHUTDOWN
+5V
+24V
0.1µF 22µF
+
23
22
K1
21
K2
20
K3
19
K4
18
K5
17
K6
16
K7
15
K8
14
UVLO
13
7
8
9
10
11
12
7-62
October 1998
Microchip MCU
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