Si4133/33G-EVB
E
VALUATION
B
OARD
Description
The Si4133/Si4133G synthesizer family evaluation
board is a complete, PC-based evaluation platform for
the following Silicon Laboratories devices and their
derivatives:
Si4133
!
Si4133G
!
Si4133G-X2
!
Si4113G-X5
!
Si4114G
!
Si4133W
!
Si4135
!
Si4136
The board includes all support circuitry necessary to
evaluate the synthesizer including a reference clock,
SMA connections for external measurement equipment,
and an interface to a personal computer for controlling
the device. The PC software is a graphical,
!
FOR THE
S
YNTHESIZER
F
AMILIES
easy-to-use interface that allows the user to directly
enter frequencies, set divider ratios, and toggle power
control options by a parallel port connection. A PC and
power supply are all that is needed for a complete
evaluation system.
Features
!
!
!
!
!
Single board evaluation platform
PC-based graphical control software included on
CD-ROM for Windows 95/98
On-board frequency reference; SMA for external
reference
SMA connections for synthesizer outputs
For use with Silicon Laboratories Si4133, Si4133G,
Si4133G-X2, Si4113G-X5, Si4114G, Si4133W,
Si4135 and Si4136 synthesizer families (TSSOP or
MLP)
Function Block Diagram
PC
PC
Interface
AUXOUT
SCLK
SDATA
SENB
RFLA
RFLB
RFLC
RFLD
RF1
RF2
JRF1
+
–
+5 V
VDD
Si41xx
RFOUT
+
–
+3 V
PW DNB
JIF1
Reference
Clock
J1EXT
IF
XIN
RFLC
IFOUT
RFLD
Preliminary Rev. 0.5 4/01
Copyright © 2001 by Silicon Laboratories
Si4133/33G-EVB-05
Si4133/33G-EVB
Functional Description
The evaluation board accommodates the synthesizer by
providing clock circuitry, a PC interface, and other
support circuitry necessary for operation.
Both the multiplexed RF output and the IF output can be
active simultaneously. Synthesizers are independently
enabled using the radio buttons in the evaluation
software.
The synthesizer IC is supplied by three different power
supplies. VDDR supplies the analog circuitry for the
RF1 and RF2 synthesizers. VDDI supplies the analog
circuitry for the IF synthesizer, and VDDD supplies the
digital prescaler, serial interface, and reference input
circuitry. Each of these supplies is bypassed to ground
with a 22 nF capacitor close to the body of the IC.
Synthesizer
The heart of the evaluation board is the Silicon
Laboratories frequency synthesizer. This section
includes the synthesizer integrated circuit (IC), external
tuning components, output matching, and power supply
decoupling circuitry.
For devices requiring an external inductor to establish
the center frequency for the RF1 and RF2 synthesizers,
the inductor is implemented with a printed trace. The IF
synthesizer inductor is set by an 0402-size chip
inductor. The inductors are set for the nominal center
frequencies shown in Table 1.
Outputs of the synthesizers are ac-coupled and
matched to a 50
Ω
load impedance. SMA connectors
are provided for easy connection to measurement
equipment or to target systems. Output JRF1 is
multiplexed between the RF1 and RF2 synthesizers and
is toggled through the evaluation software. See the
synthesizer data sheet for more detail. The second
output, JIF1, is connected to the IF synthesizer output.
PC Interface
The frequency synthesizer IC uses a serial interface for
programming. The three primary signals are serial data
(SDATA), serial clock (SCLK), and serial enable
(SENB). These are all mapped to data pins of the PC’s
parallel port. Data is read back from the IC using the
BUSY input of the parallel port and SCLK.
One additional signal, GPO, is a multipurpose signal
used to control the synthesizer’s hardware power-down
enable (PWDNB) and/or to trigger external test
equipment. The intended use is for power-up and
channel-to-channel settling time measurements. See
the "Evaluation Software" section for more detail.
Table 1. Center Frequencies
Device
Si4133
Si4133G
Si4133G-X2
Si4113G-X5
Si4114G
Si4133W
Si4135
Si4136
RF1 Center
Frequency (MHz)
1600
1600
1600
1540
1920
2360
1750
2400
RF2 Center
Frequency (MHz)
1200
1200
1200
1365
1780
1200
967
2100
IF Center
Frequency (MHz)
550
550
1080
N/A
N/A
760
170.76, 420.76
550
Clock Circuitry
The reference frequency for the synthesizer is
generated on-board by a temperature-compensated,
voltage-tuned, crystal oscillator. The circuit is flexible to
allow evaluation with an external reference source or
with different frequency oscillators in varying packages.
Header JP6 selects the reference frequency source to
the frequency synthesizer IC. Either the on-board
oscillator or the external SMA input, J8, can be
selected.
The tuning control of the oscillator, Vc, is fixed at
(Vsupply/2) by R19 and R20. C14 provides filtering for
noise reduction on the tuning input. Test points JP9 and
JP10 allow easy connection to the tuning voltage for
external frequency trimming or reference modulation.
Power Supplies
The evaluation board requires a 5 V supply at JP11 to
power the digital interface to the PC. The synthesizer’s
supply voltage can be taken from the on-board 3 V
regulator or a user-supplied voltage at JP11 depending
on the jumper setting at JP4.
2
Preliminary Rev. 0.5
Si4133/33G-EVB
AUXOUT
The AUXOUT pin of the frequency synthesizer can be
programmed for a variety of functions. The evaluation
board is normally populated so that this pin can be read
by the PC for serial reads from the IC. Other functions
can be monitored on the AUXOUT test point as well.
Refer to the appropriate synthesizer data sheet for
details of AUXOUT’s functionality and configuration.
To control PWDNB with an external generator, place a
shorting block on JP3. There should not be a shorting
block on JP2. Connect the output of the generator to
test point PWDNB. The test point labeled GND should
be connected to the shield of the cable.
The evaluation software can power down the
synthesizer through the PWDNB pin. JP2 and JP3 must
both be jumpered to use this feature. The PWDNB test
point can then be used to monitor the PWDNB signal.
Refer to the appropriate synthesizer data sheet for a
complete explanation of software and hardware power
management options.
Hardware Power Down
The hardware power-down input, PWDNB, can be
driven several different ways on the evaluation board.
The default configuration is pulled high (enabled)
through a resistive pull-up, R21. This pin may be
controlled through an external source or via evaluation
software.
Table 2. Jumper Settings
Function
Synthesizer and Reference
Clock Power
Option
On-board
regulator
User-supplied
Reference Clock
On-board
reference clock
User-supplied
PWDNB
Always high
Driven by PC
Jumper Settings
JP4: jumper REG to 3 V
JP4: jumper UNREG to
3V
JP5: jumper TCXO to ON
JP6: TCXO to XIN
Notes
No supply required on JP11 3 V pin
Supply required on JP11 3 V pin
No clock required on J8
JP5: jumper TCXO to OFF
Clock signal required on J8;
JP6: EXT to XIN
Check data sheet for requirements.
JP2: no jumper
JP3: no jumper
JP2: jumper
JP3: jumper
JP2: no jumper
JP3: jumper
Power-up/down controlled by
register settings.
PWDNB controlled by evaluation
software; Connect instrumentation
trigger to PWDNB/GND test points.
PWDNB provided by external gen-
erator connected to PWDNB/GND
test points.
Driven by external
generator
Preliminary Rev. 0.5
3
Si4133/33G-EVB
Table 3. Test Points
Function
Auxiliary Output
PC Interface
Designator
AUXOUT
SCLK
SDATA
SENB
GPO
Power
3V
GND
PWDNB
PWDNB
GND
Reference Frequency Control
VC
GND
Signal
AUXOUT signal from synthesizer
Serial clock from PC parallel port
Serial data from PC parallel port
Serial enable from PC parallel port
General purpose output from PC parallel port
Power supply to synthesizer and on-board reference oscillator
Ground reference for 3 V test point
PWDNB signal from synthesizer or GPO from PC parallel port
Ground reference for PWDNB test point
Frequency control input on TCVCXO
Ground reference for VC test point
Table 4. Connectors
Function
PC Parallel Port Interface
Power
RF Outputs
Designator
JP1
JP11
JIF1
JRF1
External Reference Input
J8
Signal
Parallel port connection to PC
5 V supply for parallel port interface and optional 3 V supply
for synthesizer and reference oscillator
IF synthesizer output, nominal 50
Ω
RF synthesizer output, nominal 50
Ω
External reference frequency input, selected by JP6
4
Preliminary Rev. 0.5
Si4133/33G-EVB
Evaluation Software
The Silicon Laboratories evaluation software is a
graphical, Windows-based user interface to the Silicon
Laboratories synthesizer family. The interface allows the
user to directly enter counter integers, frequencies, or
control bits without the need to compute and format bit-
level register information. Hardware connection to the
evaluation board is through a standard parallel port.
Window Overview
Control data may be entered in a variety of ways. Each
numerical parameter can either be entered directly from
the keyboard by selecting the box and typing or can be
stepped using the up/down arrow keys. Control bits are
selected or deselected by radio buttons.
Note:
The windows shown in these figures are specific to the
Si4133 Programmer, version 1.3.6. Evaluation soft-
ware and options may vary for other synthesizers and
software versions.
Installation
After the CD is inserted into the computer, the installer
should run automatically. The installer can also be
invoked by running the “Installer.exe” program at the
root directory of the CD. The CD contains installers for
several programs. Select the appropriate device from
the list.
Figure 1. Evaluation Software
Preliminary Rev. 0.5
5
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