SY54011R
Low Voltage 1.2V/1.8V CML 1:2 Fanout
Buffer, 3.2Gbps, 3.2GHz
General Description
The SY54011R is a fully differential, low voltage
1.2V/1.8V CML 1:2 fanout buffer. It is optimized to
provide two identical output copies with less than 15ps
of skew and less than 10ps
pp
total jitter. The SY54011R
can process clock signals as fast as 3.2GHz or data
patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled
from a 2.5V driver) as small as 100mV (200mV
PP
)
without any level-shifting or termination resistor
networks in the signal path. For AC-coupled input
interface applications, an integrated voltage reference
(V
REF-AC
) is provided to bias the VT pin. The outputs are
CML, with extremely fast rise/fall times guaranteed to be
less than 95ps.
The SY54011R operates from a 2.5V ±5% core supply
and a 1.8V or 1.2V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY54011R is part of Micrel’s
®
high-speed, Precision Edge product line.
Datasheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
∑
1.2V/1.8V CML 1:2 fanout buffer
∑
Guaranteed AC performance over temperature and
voltage:
– DC-to- > 3.2Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <15ps within-device skew
– <95ps rise/fall times
∑
Ultra-low jitter design
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter
– <1ps
RMS
random jitter
– <10ps
PP
deterministic jitter
∑
High-speed CML outputs
∑
2.5V ±5% , 1.8/1.2V ±5% power supply operation
∑
Industrial temperature range: –40°C to +85°C
®
∑
Available in 16-pin (3mm x 3mm) MLF package
Applications
∑
∑
∑
∑
Data Distribution: OC-48, OC-48+FEC
SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Functional Block Diagram
Markets
∑
∑
∑
∑
∑
∑
∑
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2008
M9999-033108-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY54011R
Ordering Information
(1)
Part Number
SY54011RMG
SY54011RMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
(2)
Package
Type
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Package Marking
011R with Pb-Free
bar-line indicator
011R with Pb-Free
bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
16-Pin MLF (MLF-16)
®
Pin Description
Pin Number
1, 4
Pin Name
IN, /IN
Pin Function
Differential Input: This input pair is the differential signal input to the device. Input
accepts differential signals as small as 100mV (200mV
PP
). Each input pin internally
terminates with 50Ω to the VT pin.
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. See “Interface Applications” subsection.
Reference Voltage: This output biases to V
CC
–1.15V. It is used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.1µF low
ESR capacitor to VCC. Maximum sink/source current is ±0.5mA. See “Input
Interface Applications” subsection.
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the V
CC
pins as possible. Supplies input and core circuitry.
Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the V
CCO
pins as possible. Supplies the output buffers.
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
CML Differential Output Pairs: Differential buffered copies of the input signal. The
output swing is typically 390mV. See “Interface Applications” subsection for
termination information.
2
VT
3
VREF-AC
5, 16
8,13
6, 7, 14, 15
10, 9
11, 12
VCC
VCCO
GND,
Exposed pad
/Q1, Q1
/Q0, Q0
March 2008
2
M9999-033108-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY54011R
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ................................. –0.5V to +3.0V
Supply Voltage (V
CCO
) ............................... –0.5V to +2.7V
V
CC
- V
CCO
.................................................................. <1.8V
V
CCO
- V
CC
.................................................................. <0.5V
Input Voltage (V
IN
) ......................................... –0.5V to V
CC
CML Output Voltage (V
OUT
)..................0.6V to V
CCO
+0.5V
Current (V
T
)
Source or sink current on VT pin .................. ±100mA
Input Current
Source or sink current on (IN, /IN) .................. ±50mA
Current (V
REF-AC
)
(4)
Source or sink current on V
REF-AC
............... ±0.5mA
Maximum operating Junction Temperature.............125°C
Lead Temperature (soldering, 20sec.) ....................260°C
Storage Temperature (T
s
) ...................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
cc
) ............................ 2.375V to 2.625V
(V
cco
)………………...……1.14V to 1.9V
Ambient Temperature (T
A
) ..................... –40°C to +85°C
(3)
Package Thermal Resistance
®
MLF
Still-air (q
JA
) .............................................. 75°C/W
Junction-to-board (y
JB
) ........................... 33°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
Parameter
Power Supply Voltage Range
Condition
V
CC
V
CCO
V
CCO
Max.
V
CC
No Load. V
CCO
45
90
IN, /IN
V
IL
with V
IH
of 1.2V
IN, /IN
V
IL
with V
IH
of 1.14V, (1.2V-5%)
see Figure 3a
see Figure 3b
1.2
0.2
1.14
0.66
0.1
0.2
V
CC
–1.3
V
CC
–1.15
Min
2.375
1.14
1.7
Typ
2.5
1.2
1.8
15
32
50
100
Max
2.625
1.26
1.9
22
42
55
110
V
CC
V
IH
–0.1
V
CC
V
IH
–0.1
1.0
2.0
V
CC
–1.0
1.28
Units
V
V
V
mA
mA
Ω
Ω
V
V
V
V
V
V
V
V
I
CC
I
CCO
R
IN
R
DIFF_IN
V
IH
V
IL
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF-AC
V
T_IN
Power Supply Current
Power Supply Current
Input Resistance
(IN-to-V
T
, /IN-to-V
T
)
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
(|IN - /IN|)
Output Reference Voltage
Voltage from Input to V
T
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
y
JB
and
q
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
March 2008
3
M9999-033108-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY54011R
CML Outputs DC Electrical Characteristics
(6)
V
CCO
= 1.14V to 1.26V R
L
= 50Ω to V
CCO,
V
CCO
= 1.7V to 1.9V, R
L
= 50Ω to V
CCO
or 100Ω across the outputs,
V
CC
= 2.375V to 2.625V. T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
OH
V
OUT
V
DIFF_OUT
R
OUT
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established
Parameter
Output HIGH Voltage
Output Voltage Swing
Differential Output Voltage Swing
Output Source Impedance
Condition
R
L
= 50Ω to V
CCO
See Figure 3a
See Figure 3b
Min
V
CCO
-0.020
300
600
45
Typ
V
CCO
-0.010
390
780
50
Max
V
CCO
475
950
55
Units
V
mV
mV
Ω
AC Electrical Characteristics
V
CCO
= 1.14V to 1.26V R
L
= 50Ω to V
CCO,
V
CCO
= 1.7V to 1.9V, R
L
= 50Ω to V
CCO
or 100Ω across the outputs,
V
CC
= 2.375V to 2.625V. T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
f
MAX
t
PD
t
Skew
t
Jitter
Parameter
Maximum Frequency
Propagation Delay
Within Device Skew
Part-to-Part Skew
Data
Clock
t
R
t
F
Random Jitter
Deterministic Jitter
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Notes:
7.
8.
9.
Within device skew is measured between two different outputs under identical input transitions.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Random jitter is measured with a K28.7 pattern, measured at
≤
f
MAX
.
23
Condition
NRZ Data
V
OUT
> 200mV
IN-to-Q
Figure 1a
Note 7
Note 8
Note 9
Note 10
Note 11
Note 12
At full output swing.
Differential I/O
Clock
Min
3.2
3.2
150
Typ
Max
Units
Gbps
GHz
205
3
300
15
75
1
10
1
10
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
ps
%
30
47
60
95
53
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 –1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤
f
MAX
(device), no more than one output edge in 10 output edges will deviate by
more than the specified peak-to-peak jitter value.
12
March 2008
4
M9999-033108-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY54011R
Interface Applications
For Input Interface Applications see Figures 4a-f and
for CML Output Termination see Figures 5a-d.
CML Output Termination with VCCO 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50Ω-to-1.2V, DC-coupled, not 100Ω differentially
across the outputs.
If AC-coupling is used, Figure 5d, terminate into 50Ω-
to-1.2V before the coupling capacitor and then
connect to a high value resistor to a reference
voltage.
Do not AC couple with internally terminated receiver.
For example, 50Ω ANY-IN input. AC-coupling will
offset the output voltage by 200mV and this offset
voltage will be too low for proper driver operation.
Any unused output pair needs to be terminated when
VCCO is 1.2V, do not leave floating.
CML Output Termination with VCCO 1.8V
For VCCO of 1.8V, Figure 5a and Figure b, terminate
with either 50Ω-to-1.8V or 100Ω differentially across
the outputs. AC- or DC-coupling is fine.
Input AC Coupling
The SY54011R input can accept AC coupling from
any driver. Tie VT to VREF-AC and bypass with a
0.1µF capacitor as shown in Figures 4c and 4d.
Timing Diagrams
Figure 1a. Propagation Delay
March 2008
5
M9999-033108-A
hbwhelp@micrel.com
or (408) 955-1690
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