FX-400
Low Jitter Frequency Translator
Previous Part Number FX-424
FX-400
Description
The FX-400 is a precision quartz-based frequency translator used to translate an input frequency such as 8 kHz, 1.544 MHz, 2.048
MHz, 19.44 MHz etc. to any specific frequency from 1.544 MHz to 1.0 GHz. The FX-400 can perform either up or down frequency
conversion. The FX-400’s superior jitter performance is achieved through the use of a precision VCXO or VCSO. With the use of an
external multiplexer, up to 4 different input clocks can be translated to a common output frequency.
Features
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•
•
•
•
•
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Quartz-based PLL for Ultra-Low Jitter
Frequency Translation up to 1 GHz
Accepts up to 4 ext.-muxed clock inputs
LVCMOS / LVDS / LVPECL Inputs compatible
Differential LVPECL /LVDS or LVCMOS Output
Lock Detect / Loss of Signal Alarms
Output Disable
20.3 x 13.7 x 5.1 mm SMT package
RoHS/Lead Free Compliant
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•
•
•
•
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Applications
Wireless Infrastructure
10 Gigabit FC
10GbE LAN / WAN
OADM and IP Routers
Test Equipment
Military Communications
Block Diagram
VCC
(14)
FIN
1
FIN
2
FIN
3
FIN
4
FIN
(13)
LD
(10)
Phase
Detector
& LD
VMON
(5)
Loop Filter
VCSO
(8)
FOUT
1
(9)
CFOUT
1
÷
μ Controller
SEL0 (1)
SEL1 (2)
÷
GND
(3, 7, 11, 12)
OD
(6)
Figure 1. Functional block diagram
Page 1 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009
Performance Specifications
Table 1. Electrical Performance
Parameter
Frequency
1, 2, 3
Input Frequency
Capture Range
Output Frequency
Supply
Voltage
2, 3
Current (No Load)
3
Input Signal
2, 3
LVCMOS
LVDS
LVPECL
LVCMOS Output (Option A)
2, 3
Differential Output (Options C and D)
2, 3, 4, 5
Mid Level - LVPECL
Swing - LVPECL
Mid Level - LVDS
Swing - LVDS
Rise Time
Fall Time
Symmetry
SSB Phase Noise, Fout = 155.52/622.08
5, 6
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offfset
1 MHz Offset
10 MHz Offset
Jitter Generation
5, 6
155.52 MHz (12kHz - 20MHz BW)
622.08 MHz (12kHz - 20 MHz BW)
Operating Temperature (Options T of E)
1 ,3
V
CC
-1.4
450
V
CC
-2.4
250
t
R
t
F
SYM
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
J
Φ
J
T
OP
Symbol
F
IN
APR
F
OUT
V
CC
I
CC
F
IN
F
IN
F
IN
Min
0.008
±40
1.544
3.13
Typical
Maximum
800
1000
Units
MHz
ppm
MHz
V
mA
3.3
60
CMOS
LVDS
LVPECL
LVCMOS
V
CC
-1.25
600
V
CC
-2.3
410
0.5
0.5
50
-64/-27
-95/-55
-123/-123
-143/-110
-146/-130
-146/-146
-146/-146
0.30
0.12
0 to 70 or -40 to 85
3.46
100
V
CC
-1.0
950
V
CC
-2.5
450
45
55
V
mV p-p
V
mV p-p
ns
ns
%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps RMS
ps RMS
0C
1.
2.
3.
4.
5.
6.
See Standard Frequencies and Ordering Information.
Parameters are tested with production test circuit below (Fig 2).
Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature.
Measured from 20% to 80% of a full output swing (Fig 3).
Not tested in production, guaranteed by design, verified at qualification.
The FX-400 phase noise and jitter performance can be optimized for specific applications. Please consult with Vectron’s Application Engineers
for more information.
Page 2 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied
at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to
absolute maximum ratings for extended periods may adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temp/TIme
Symbol
V
DD
T
STR
T
LS
Ratings
6
-55 to 125
260/40
Unit
V
0C
0C/sec
Reliability
The FX-400 is capable of meeting the following qualification tests
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitrry has been designed into the the FX-400, proper precautions should be taken when handling
and mounting. VI employs a human body model and a charged-device model (CDM) for ESD susceptibility testing and design
protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry
wide standard has been adopted for the CDM, a standard HBM of resistance=1.5Kohms and capacitance = 100pF is widely used
and therefore can be used for comparison purposes
Table 4. Predicted ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
500 V
500 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
Page 3 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009
Reflow Profile
Table 5. Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217 0C
Time To Peak Temperature
Time At 260 0C
Ramp Down
Symbol
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
3 0C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6 0C/sec Max
The FX-400 is qualified to meet the JEDEC stan-
dard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-Free
small body requirements. The temperatures refer
to the topside of the package, measured on the
package body surface. The FX-400 should not
be subjected to a wash process that will immerse
it in solvents. NO CLEAN is the recommended
procedure. The FX-400 has been designed for pick
and place reflow soldering. The FX-400 may be
reflowed once and should not be reflowed in the
inverted position.
Figure 4. Suggested IR Profile
Tape and Reel
Table 6. Tape and Reel Information
Tape Dimensions (mm)
W
44
F
20.2
Do
1.5
Po
4
P1
20
A
330
B
1.5
Reel Dimensions (mm)
C
13
D
20.2
N
100
W1
44.4
W2
50.4
#/Reel
200
Figure 5. Tape and Reel
Page 4 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009
Pin Configuration
Figure 6. Pin Configuration
Table 7. Pin Functions
Pin #
1
2
3
4
5
VMON
O
Symbol
SEL0
SEL1
GND
I/O
I
I
GND
Level
LVCMOS
LVCMOS
Supply
Frequency Select
*
(See Table 8)
Frequency Select
*
(See Table 8)
Case and Electrical Ground
Not present
Function
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input frequency may
be out of range if the voltage exceeds these levels
LVCMOS
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Case and Electrical Ground
Frequency Output
Complementary Frequency Output – Note for LVCMOS option this pad will be tied to
GND.
Lock Detect
Locked = Logic “1”
Loss of Signal = Logic “0”
Case and Electrical Ground
Case and Electrical Ground
6
OD
I
7
8
9
10
GND
FOUT
CFOUT
LD
GND
O
O
O
Supply
LCPECL. LVDS or
LVCMOS
LVPECL, LVDS or
LVCMOS
LVCMOS
11
12
GND
GND
GND
GND
Supply
Supply
13
14
*
FIN
VCC
I
VCC
LVCMOS or
LVPECL
Supply
Input Frequency – AC Coupled
Power Supply Voltage (3.3 V ±5%)
For applications requiring two to four input frequencies, Vectron will assign a unique part number and the Input Frequency versus SEL[1:0] settings will be pro-
vided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied to ground.
Table 8. Control Logic (LVCMOS)
SEL0
0
0
1
1
SEL1
0
1
0
1
Reference Clock Input
F
1
F
2
F
3
F
4
Page 5 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 01Apr2009
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