FM33256B
3V Integrated Processor Companion with F-RAM
Features
High Integration Device Replaces Multiple Parts
•
Serial Nonvolatile Memory
•
Real-time Clock (RTC) with Alarm
•
Low V
DD
Detection Drives Reset
•
Watchdog Window Timer
•
Early Power-Fail Warning/NMI
•
16-bit Nonvolatile Event Counter
•
Serial Number with Write-lock for Security
Ferroelectric Nonvolatile RAM
•
256Kb F-RAM
•
High Endurance 100 Trillion (10
14
) Read/Writes
•
38 year Data Retention (+75°C)
•
NoDelay™ Writes
Real-time Clock/Calendar
•
Backup Current at 2V, 1.15
µA
(max.) at +25C
•
Seconds through Centuries in BCD format
•
Tracks Leap Years through 2099
•
Uses Standard 32.768 kHz Crystal
•
Software Calibration
•
Supports Battery or Capacitor Backup
Processor Companion
•
Active-low Reset Output for V
DD
and Watchdog
•
Programmable Low-V
DD
Reset Thresholds
•
Manual Reset Filtered and Debounced
•
Programmable Watchdog Window Timer
•
Nonvolatile Event Counter Tracks System
Intrusions or other Events
•
Comparator for Power-Fail Interrupt or Other Use
•
64-bit Programmable Serial Number with Lock
Fast SPI Interface
•
Up to 16 MHz Maximum Bus Frequency
•
RTC, Supervisor Controlled via SPI Interface
•
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Easy to Use Configuration
•
Operates from 2.7 to 3.6V
•
Small Footprint “Green” 14-pin SOIC (-G)
•
Low Operating Current
•
-40°C to +85°C Operation
•
Underwriters Laboratory (UL) Recognized
Description
The FM33256B device integrates F-RAM memory
with the most commonly needed functions for
processor-based systems. Major features include
nonvolatile memory, real-time clock, low-V
DD
reset,
watchdog timer, nonvolatile event counter, lockable
64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI)
interrupt or other purpose. The device operate from
2.7 to 3.6V.
The FM33256B provides 256Kb memory capacity of
nonvolatile F-RAM. Fast write speed and unlimited
endurance allow the memory to serve as extra RAM
or conventional nonvolatile storage. This memory is
truly nonvolatile rather than battery backed.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low V
DD
condition or a watchdog timeout. /RST goes
active when V
DD
drops below a programmable
threshold and remains active for 100 ms (max.) after
V
DD
rises above the trip point. A programmable
watchdog timer runs from 60 ms to 1.8 seconds. The
timer may also be programmed for a delayed start,
which functions as a window timer. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host within
the time window. A flag-bit indicates the source of
the reset.
A comparator on PFI compares an external input pin
to the onboard 1.5V reference. This is useful for
generating a power-fail interrupt (NMI) but can be
used for any purpose. The family also includes a
programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers an
event counter that tracks the number of rising or
falling edges detected on a dedicated input pin. The
counter can be programmed to be non-volatile under
V
DD
power or battery-backed using only V
BAK
. If
V
BAK
is connected to a battery or capacitor, then
events will be counted even in the absence of V
DD
.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
www.ramtron.com
Page 1 of 28
FM33256B SPI Companion w/ FRAM
Pin Configuration
CS
SO
CNT
VBAK
X2
X1
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
ACS
SCK
SI
PFO
RST
PFI
Pin Name
/CS
SCK
SI
SO
PFI
PFO
CNT
ACS
/RST
X1, X2
VDD
VBAK
VSS
Function
Chip Select
Serial Clock
Serial Data Input
Serial Data Output
Power Fail Input
Power Fail Output (NMI)
Event Counter Input
Alarm/Calibration/SqWave
Reset Input/Output
External Crystal Connections
(optional)
Supply Voltage
Battery-Backup Supply
Ground
Pin Descriptions
Pin Name
/CS
Type
Input
Pin Description
Chip Select: This active low input activates the device. When high, the device enters low-
power standby mode, ignores the SCK and SI inputs, and the SO output is tri-stated.
When low, the device internally activates the SCK signal. A falling edge on /CS must
occur prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the
rising edge and outputs occur on the falling edge. Since the device is static, the clock
frequency may be any value between 0 and 16 MHz and may be interrupted at any time.
Serial Input: All data is input to the device on this pin. The pin is sampled on the rising
edge of SCK and is ignored at other times. It should always be driven to a valid logic level
to meet I
DD
specifications. The SI pin may be connected to SO for a single pin data
interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-stated
at all other times. Data transitions are driven on the falling edge of the serial clock. The
SO pin may be connected to SI for a single pin data interface.
Event Counter Input: This input increments the counter when an edge is detected on this
pin. The polarity is programmable and the counter value is nonvolatile or battery-backed,
depending on the mode. This pin should be tied to ground if unused.
Alarm/Calibration/SquareWave: This is an open-drain output that requires an external
pullup resistor. In normal operation, this pin acts as the active-low alarm output. In
Calibration mode, a 512 Hz square-wave is driven out. In SquareWave mode, the user
may select a frequency of 1, 512, 4096, or 32768 Hz to be used as a continuous output.
The SquareWave mode is entered by clearing the AL/SW and CAL bits in register 18h.
32.768 kHz crystal connection (see Crystal Type section for suggestions). See AN407
app. note for details on how to connect external oscillator.
Reset: This active-low output is open drain with weak pull-up. It is also an input when
used as a manual reset. This pin should be left floating if unused.
Early Power-fail Input: Typically connected to an unregulated power supply to detect an
early power failure. This pin must be tied to ground if unused.
Early Power-fail Output: This pin is the early power-fail output and is typically used to
drive a microcontroller NMI pin. PFO drives low when the PFI voltage is <1.5V.
Backup supply voltage: A 3V battery or a large value capacitor. If no backup supply is
used, this pin should be tied to V
SS
and the VBC bit should be cleared. The trickle charger
is UL recognized and ensures no excessive current when using a lithium battery.
Supply Voltage.
Ground
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
SCK
Input
SI
Input
SO
Output
CNT
Input
ACS
Output
X1, X2
/RST
PFI
PFO
VBAK
I/O
I/O
Input
Output
Supply
VDD
VSS
Supply
Supply
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
www.ramtron.com
Page 2 of 28
FM33256B SPI Companion w/ FRAM
CS
SCK
SI
SO
SPI
Interface
FRAM
Array
LockOut
RST
Manual Reset
Watchdog
LV Detect
Special
Function
Registers
S/N
RTC Cal.
RTC Registers
X1
PFI
PFO
CNT
+
RTC
X2
-
1.5V
Event
Counter
Alarm
V
SW
VDD
-
+
Alarm
512Hz/SqW
ACS
Switched Power
VBAK
Nonvolatile
Battery Backed
NV/BB User Programmable
Figure 1. Block Diagram
Ordering Information
Base
Configuration
FM33256B
FM33256B
Memory
Size
256Kb
256Kb
Operating
Voltage
2.7-3.6V
2.7-3.6V
Max. Clock
Freq.
16 MHz
16 MHz
Reset Thresholds
2.6V, 2.75, 2.9, 3.0V
2.6V, 2.75, 2.9, 3.0V
Ordering Part Number
FM33256B-G
FM33256B-GTR (tape&reel)
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 3 of 28
FM33256B SPI Companion w/ FRAM
Overview
The FM33256B device combines a serial nonvolatile
RAM with a real-time clock (RTC) and a processor
companion. The companion is a highly integrated
peripheral including a processor supervisor, analog
comparator, a nonvolatile counter, and a serial
number.
The
FM33256B
integrates
these
complementary but distinct functions under a
common interface in a single package. The product is
organized as two logical devices. The first is a
memory and the second is the companion which
includes all the remaining functions. From the system
perspective they appear to be two separate devices
with unique op-codes on the serial bus.
The memory is organized as a standalone nonvolatile
SPI memory using standard op-codes. The real-time
clock and supervisor functions are accessed under
their own op-codes. The clock and supervisor
functions are controlled by 30 special function
registers. The RTC/alarm and some control registers
are maintained by the power source on the VBAK
pin, allowing them to operate from battery or backup
capacitor power when V
DD
drops below a set
threshold. Each functional block is described below.
Processor Companion
In addition to nonvolatile RAM, the FM33256B
incorporates a real-time clock with alarm and highly
integrated processor companion. The companion
includes a low-V
DD
reset, a programmable watchdog
timer, a 16-bit nonvolatile event counter, a
comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic
functions: Detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. The FM33256B has a reset pin (/RST) to
drive a processor reset input during power faults,
power-up, and software lockups. It is an open drain
output with a weak internal pull-up to V
DD
. This
allows other reset sources to be wire-OR’d to the
/RST pin. When V
DD
is above the programmed trip
point, /RST output is pulled weakly to V
DD
. If V
DD
drops below the reset trip point voltage level (V
TP
),
the /RST pin will be driven low. It will remain low
until V
DD
falls too low for circuit operation which is
the V
RST
level. When V
DD
rises again above V
TP
,
/RST continues to drive low for at least 50 ms (t
RPU
)
to ensure a robust system reset at a reliable V
DD
level.
After t
RPU
has been met, the /RST pin will return to
the weak high state. While /RST is asserted, serial
bus activity is locked out even if a transaction
occurred as V
DD
dropped below V
TP
. A memory
operation started while V
DD
is above V
TP
will be
completed internally.
Table 1 below shows how bits VTP(1:0) control the
trip point of the low-V
DD
reset. They are located in
register 18h, bits 0 and 1. The reset pin will drive
low when V
DD
is below the selected V
TP
voltage, and
the SPI interface and F-RAM array will be locked
out. Figure 2 illustrates the reset operation in
response to a low V
DD
.
VTP Setting
2.6V
2.75V
2.9V
3.0V
VTP1
0
0
1
1
VTP0
0
1
0
1
Memory Operation
The FM33256B is available with 256Kb of memory.
The device uses two-byte addressing for the memory
portion of the chip. This makes the device software
compatible with its standalone memory counterparts,
such as the FM25W256.
Memory is organized in bytes. The 256Kb memory is
32,768 x 8. The memory is based on F-RAM
technology. Therefore it can be treated as RAM and
is read or written at the speed of the SPI bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The SPI protocol is described
on page 18.
The memory array can be write-protected by
software. Two bits (BP0, BP1) in the Status Register
control the protection setting. Based on the setting,
the protected addresses cannot be written. The Status
Register & Write Protection is described in more
detail on page 20.
Table 1.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 4 of 28
FM33256B SPI Companion w/ FRAM
VDD
VTP
t
RPU
RST
timer as described above. This assures that the full
timeout is provided immediately after enabling. The
watchdog is disabled when V
DD
drops below V
TP
.
Note setting the EndTime timeout setting to all
zeroes (00000b) disables the timer to save power.
The listing below summarizes the watchdog bits.
Watchdog StartTime
Watchdog EndTime
Watchdog Enable
Watchdog Restart
Watchdog Flags
WDST4-0
WDET4-0
WDE
WR3-0
EWDF,
LWDF
0Bh, bits 4-0
0Ch, bits 4-0
0Ch, bit 7
0Ah, bits 3-0
09h, bit 7
09h, bit 6
Figure 2. Low V
DD
Reset
A watchdog timer can also be used to drive an active
reset signal. The watchdog is a free-running
programmable timer. The timeout period can be
software programmed from 60 ms to 1.8 seconds in
60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
100 ms
clock
Timebase
WR3-0 = 1010b
to restart
Down Counter
Watchdog
Timer Settings
/RST
WDE
Figure 3. Watchdog Timer
The watchdog also incorporates a window timer
feature that allows a delayed start. The starting time
and ending time defines the window and each may be
set independently. The starting time has 25 ms
resolution and 0 ms to 775 ms range.
Watchdog
Restart
Start
Time
End
Time
The programmed StartTime value is a guaranteed
maximum time while the EndTime value is a
guaranteed minimum time, and both vary with
temperature and V
DD
voltage. The watchdog has two
additional controls associated with its operation. The
nonvolatile enable bit WDE allows the /RST to go
active if the watchdog reaches the timeout without
being restarted. If a reset occurs, the timer will restart
on the rising edge of the reset pulse. If WDE is not
enabled, the watchdog timer still runs but has no
effect on /RST. The second control is a nibble that
restarts the timer, thus preventing a reset. The timer
should be restarted after changing the timeout value.
This procedure must be followed to properly load the
watchdog registers:
1.
2.
3.
Address
Write the StartTime value
0Bh
Write the EndTime value and WDE=1 0Ch
Issue a Restart command
0Ah
Window
The restart command in step 3 must be issued before
t
DOG2
, which was programmed in step 2. The window
timer starts counting when the restart command is
issued.
100 ms (max)
RST
Figure 4. Window Timer
The watchdog EndTime value is located in register
0Ch, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 0Ah. Writing the correct
pattern will also cause the timer to load new timeout
values. Writing other patterns to this address will not
affect its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
Manual Reset
The /RST is a bi-directional signal allowing the
FM33256B to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms (max.). This effectively filters and de-
bounces a reset switch. After this timeout (t
RPU
), the
user may continue pulling down on the /RST pin, but
SPI commands will not be locked out.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 5 of 28
消费电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
