ADVANCED INFORMATION
MX26L6420
64M-BIT [4M x 16] CMOS
MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
• 4,194,304 x 16 byte structure
• Single Power Supply Operation
- 3.0 to 3.6 volt for read, erase and program opera-
tions
• Low Vcc write inhibit is equal to or less than 2.5V
• Compatible with JEDEC standard
• High Performance
- Fast access time: 90/100/120ns (typ.)
- Fast program time: 140s/chip (typ.)
- Fast erase time: 150s/chip (typ.)
• Low Power Consumption
- Low active read current: 17mA (typ.) at 5MHz
- Low standby current: 30uA (typ.)
• Provides a 512 word area for code or data that can be
permanently protected. Once this sector is protected,
it is prohibited to program or erase within the sector
again.
• Minimum 100 erase/program cycle
• Status Reply
- Data polling & Toggle bits provide detection of pro-
gram and erase operation completion
• 12V ACC input pin provides accelerated program ca-
pability
• Output voltages and input voltages on the device is
determined by the voltage on the VI/O pin.
- VI/O voltage range:1.65V~3.6V
• 10 years data retention
• Package
- 44-Pin SOP
- 48-Pin TSOP
GENERAL DESCRIPTION
The MX26L6420 is a 64M bit MTP EPROM
TM
organized
as 4M bytes of 16 bits. MXIC's MTP EPROM
TM
offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX26L6420 is packaged in
44-pin SOP and 48-pin TSOP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX26L6420 offers access time as fast as
90ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX26L6420 has separate chip enable (CE) and output
enable OE controls. MXIC's MTP EPROM
TM
augment
EPROM functionality with in-circuit electrical erasure and
programming. The MX26L6420 uses a command register
to manage this functionality.
MXIC's MTP EPROM
TM
technology reliably stores
memory contents even after 100 erase and program
cycles. The MXIC cell is designed to optimize the erase
and program mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling.
The MX26L6420 uses a 3.0V to 3.6V VCC supply to
perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epiprocess. Latch-up protection
is proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC +1V.
P/N:PM0823
REV. 0.9.1, NOV. 20, 2002
1
MX26L6420
PIN CONFIGURATION
44 SOP
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WE
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
ACC
VCC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
I/O
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MX26L6420
MX26L6420
PIN DESCRIPTION
SYMBOL
A0~A21
Q0~Q15
CE
WE
OE
RESET
VCC
ACC
V I/O
GND
NC
PIN NAME
Address Input
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Hardware Reset Pin, Active Low
Power supply
Hardware Acceleration Pin
I/O power supply (For 48 TSOP only)
Device Ground
Pin Not Connected Internally
LOGIC SYMBOL
21
A0-A21
Q0-Q15
16
CE
OE
WE
RESET
ACC
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REV. 0.9.1, NOV. 20, 2002
2
MX26L6420
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX26L6420
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A21
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
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3
MX26L6420
AUTOMATIC PROGRAMMING
The MX26L6420 is word programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the MX26L6420 is around 140 seconds.
ming and erase operations. All address are latched on
the falling edge of WE or CE, whichever happens later.
All data are latched on rising edge of WE or CE, which-
ever happens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX26L6420 electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron injec-
tion.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is around 150 sec-
onds. The Automatic Erase algorithm automatically pro-
grams the entire array prior to electrical erase. The tim-
ing and verification of electrical erase are controlled in-
ternally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
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REV. 0.9.1, NOV. 20, 2002
4
MX26L6420
Table 1
BUS OPERATION(1)
Operation
Read
Write(Note 1)
Standby
Output Disable
Reset
CE
L
L
VCC±0.3V
L
X
OE
L
H
X
H
X
WE
H
L
X
H
X
RESET
H
H
VCC±0.3V
H
L
Address
A
IN
A
IN
X
X
X
Q15~Q0
D
OUT
D
IN
High-Z
High-Z
High-Z
Legend:
L=Logic LOW=V
IL
,H=Logic High=V
IH
,V
ID
=12.0±0.5V,X=Don't Care, A
IN
=Address IN, D
IN
=Data IN, D
OUT
=Data OUT
Notes:
1. When the ACC pin is at V
HH
, the device enters the accelerated program mode. See "Accelerated Program Operations"
for more information.
Table 2. AUTOSELECT CODES (High Voltage Method)
A5
Operation
Read Silicon ID
Manufactures Code
Read Silicon ID
Device Code
Secured Silscon
Sector Indicator
Bit (Q7)
L
L
H
H
H
X
L
X
V
ID
X
X
xx88h
(factory locked)
xx08h
(non-factory locked)
L
L
H
H
L
X
L
X
V
ID
X
X
22FCH
CE
L
OE
L
WE
H
A0
L
A1
L
to
A2
X
L
A6
A8
to
A7
X
V
ID
A9
A14
to
A10
X
X00
C2H
A15~A21
Q15~Q0
P/N:PM0823
REV. 0.9.1, NOV. 20, 2002
5
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