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PI6C2405A-1HW

产品描述6C SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
产品类别逻辑    逻辑   
文件大小304KB,共7页
制造商Pericom Semiconductor Corporation (Diodes Incorporated)
官网地址https://www.diodes.com/
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PI6C2405A-1HW概述

6C SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

PI6C2405A-1HW规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Pericom Semiconductor Corporation (Diodes Incorporated)
零件包装代码SOIC
包装说明SOP, SOP8,.25
针数8
Reach Compliance Codecompli
ECCN代码EAR99
系列6C
输入调节STANDARD
JESD-30 代码R-PDSO-G8
JESD-609代码e0
长度4.9 mm
逻辑集成电路类型PLL BASED CLOCK DRIVER
最大I(ol)0.012 A
湿度敏感等级1
功能数量1
反相输出次数
端子数量8
实输出次数5
最高工作温度70 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP8,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)240
电源3.3 V
传播延迟(tpd)0.3 ns
认证状态Not Qualified
Same Edge Skew-Max(tskwd)0.2 ns
座面最大高度1.75 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度3.9 mm
最小 fmax133 MHz

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PI6C2405A
Zero-Delay Clock Buffer
Features
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 300ps
Internal feedback allows outputs to be synchronized
to the clock input
5V tolerant input*
Spread spectrum clock ready
Operates at 3.3V V
DD
Packaging (Pb-free & Green available):
-8-pin, 150-mil SOIC (W)
-8-pin, 173-mil TSSOP (L)
Description
The PI6C2405A is a PLL based, zero-delay buffer, with the ability
to distribute five outputs of up to 133MHz at 3.3V. All the outputs
are distributed from a single clock input CLKIN and output OUT0
performs zero delay by connecting a feedback to PLL.
An internal feedback on OUT0 is used to synchronize the out-
puts to the input; the relationship between loading of this signal
and the outputs determines the input-output delay. PI6C2405A
is able to track spread spectrum clocking for EMI reduction.
PI6C2405A is characterized for both commercial and industrial
operation.
PI6C2405A-1H is a high-drive version of PI6C2405A-1
* CLKIN must reference the same voltage thresholds for the PLL to
deliver zero delay skewing
Block Diagram
Pin Configuration
CLKIN
PLL
OUT
0
OUT
1
OUT
2
OUT
3
CLKIN
OUT
2
OUT
1
GND
1
2
3
4
8
7
6
5
OUT
0
OUT
4
V
DD
OUT
3
PI6C2405A(–1, –1H)
OUT
4
Pin Description
Pin
1
2, 3, 5, 7
4
6
8
Signal
CLKIN
OUT[1-4]
GND
V
DD
OUT0
Description
Input clock reference frequency (weak pull-down)
Clock Outputs
Ground
3.3V Supply
Clockoutput, internal PLL feedback (weak pull-down)
1
PS8592D
09/22/04

 
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