Datasheet> 器件分类 > 无源元件> 振荡器> SIT5155AICFK825IR-24.553500T

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SIT5155AICFK825IR-24.553500T: 产品描述Clipped Sine Output Oscillator, 24.5535MHz Nom,; 产品类别无源元件振荡器; 文件大小1MB，共38页; 制造商SiTime; 标准

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SIT5155AICFK825IR-24.553500T概述

Clipped Sine Output Oscillator, 24.5535MHz Nom,

SIT5155AICFK825IR-24.553500T规格参数

参数名称	属性值
是否Rohs认证	符合
Objectid	7214576459
包装说明	LCC10,.12X.2,53/47/43
Reach Compliance Code	compliant
其他特性	ENABLE/DISABLE FUNCTION
老化	1 PPM/FIRST YEAR
频率调整-机械	NO
频率偏移/牵引率	10 ppm
频率稳定性	0.5%
JESD-609代码	e4
安装特点	SURFACE MOUNT
端子数量	10
标称工作频率	24.5535 MHz
最高工作温度	85 °C
最低工作温度	-40 °C
振荡器类型	CLIPPED SINE
输出阻抗	10000 Ω
输出电平	0.8 V
封装主体材料	CERAMIC
封装等效代码	LCC10,.12X.2,53/47/43
物理尺寸	5.15mm x 3.35mm x 1.06mm
最大供电电压	2.75 V
最小供电电压	2.25 V
标称供电电压	25 V
表面贴装	YES
端子面层	GOLD OVER NICKEL

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SiT5155

Description

±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS

Features



The

SiT5155

is a ±0.5 ppm MEMS Super-TCXO that is

engineered for high reliability, GNSS-based precision

positioning and timing applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5155 delivers the best dynamic performance for timing

stability in the presence of environmental stressors such as

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5155 offers three device configurations that can be

ordered using

Ordering Codes

for:

1) TCXO with non-pullable output frequency,

2) VCTCXO allowing voltage control of output

frequency, and

3) DCTCXO, enabling digital control of output frequency

using an I C interface, pullable to 5 ppt (parts per

trillion) resolution.

The SiT5155 can be factory programmed for specific

combinations of frequency, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.



12 frequencies from 10 MHz to 40 MHz

Factory programmable options for short lead time

Best dynamic stability under airflow, thermal shock



±0.5 ppm stability across temperature



±15 ppb/°C typical

frequency slope (ΔF/ΔT)

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I C



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5V, 2.8V, 3.0V and 3.3V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications



Precision GNSS systems

Microwave backhaul

Professional audio and video equipment

Network routers and switches

Storage and servers

Test and measurement

Block Diagram

5.0 mm x 3.2 mm Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5155 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 1.03

March 28, 2020

www.sitime.com

SiT5155

±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 13

Typical Performance Plots ......................................................................................................................................................... 14

Architecture Overview ................................................................................................................................................................ 16

Frequency Stability ............................................................................................................................................................. 16

Output Frequency and Format ............................................................................................................................................ 16

Output Frequency Tuning ................................................................................................................................................... 16

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17

Device Configurations ................................................................................................................................................................ 17

TCXO Configuration ........................................................................................................................................................... 17

VCTCXO Configuration ...................................................................................................................................................... 18

DCTCXO Configuration ...................................................................................................................................................... 19

VCTCXO-Specific Design Considerations ................................................................................................................................. 20

Linearity .............................................................................................................................................................................. 20

Control Voltage Bandwidth ................................................................................................................................................. 20

FV Characteristic Slope K

................................................................................................................................................. 20

Pull Range, Absolute Pull Range ........................................................................................................................................ 21

DCTCXO-Specific Design Considerations ................................................................................................................................. 22

Pull Range and Absolute Pull Range .................................................................................................................................. 22

Output Frequency ............................................................................................................................................................... 23

I C Control Registers .......................................................................................................................................................... 25

Register Descriptions.......................................................................................................................................................... 25

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW)......................................... 26

[15]

Register Address: 0x02. DIGITAL PULL RANGE CONTROL ......................................................................................... 27

Serial Interface Configuration Description .......................................................................................................................... 28

Serial Signal Format ........................................................................................................................................................... 28

Parallel Signal Format ........................................................................................................................................................ 29

Parallel Data Format ........................................................................................................................................................... 29

I C Timing Specification ...................................................................................................................................................... 31

I C Device Address Modes ................................................................................................................................................. 32

Schematic Example ............................................................................................................................................................ 33

Dimensions and Patterns ........................................................................................................................................................... 34

Layout Guidelines ...................................................................................................................................................................... 35

Manufacturing Guidelines .......................................................................................................................................................... 35

Additional Information ................................................................................................................................................................ 36

Revision History ......................................................................................................................................................................... 37

Rev 1.03

Page 3 of 38

www.sitime.com

SIT5155AICFK825IR-24.553500T

SIT5155AICFK825IR-24.553500T概述

SIT5155AICFK825IR-24.553500T规格参数

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