CYF0018V
CYF0036V
CYF0072V
18/36/72-Mbit Programmable FIFOs
:)8/36/72-Mbit Programmable FIFOs
Features
■
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The user-programmable registers
enable user to configure the device operation as desired. The
device also offers a simple and easy-to-use interface to reduce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including multiprocessor
interfaces, video and image processing, networking and
telecommunications, high-speed data acquisition, or any system
that needs buffering at high speeds across different clock
domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. If writes and inputs are
enabled (WEN & IE), data on the write port gets written into the
device at the rising edge of write clock. Enabling reads and
outputs (REN & OE) fetches data on the read port at every rising
edge of read clock. Both reads and writes can occur
simultaneously at different speeds provided the ratio between
read and write clock is in the range of 0.5 to 2. Appropriate flags
are set whenever the FIFO is empty, almost-empty, half-full,
almost-full or full.
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All product features and specs are common to all densities
(CYF0072V, CYF0036V, and CYF0018V). All descriptions are
given assuming the 72Mbit (CYF0072V) device is operated in
× 36 mode. They are valid for other densities (CYF0036V, and
CYF0018V) and all port sizes × 9, × 12, × 16, × 18, × 20, × 24
and × 32 unless otherwise specified. The only difference will be
in the input and output bus width.
Table 1 on page 7
shows the
part of bus with valid data from D[35:0] and Q[35:0] in × 9, × 12,
× 16, × 18, × 20, × 24, × 32 and × 36 modes.
For a complete list of related documentation,
click here.
Memory organization
❐
Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit, and 72-Mbit
❐
Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
Up to 133-MHz clock operation
Unidirectional operation
Independent read and write ports
❐
Supports simultaneous read and write operations
❐
Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐
Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
Input and output enable control for write mask and read skip
operations
Mark and retransmit: resets read pointer to user marked
position
Empty, full, half-full, and programmable almost-empty and
almost-full status flags with configured offsets
Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
Configure programmable flags and registers through serial or
parallel modes
Separate serial clock (SCLK) input for serial programming
Master reset to clear entire FIFO
Partial reset to clear data but retain programmable settings
Joint test action group (JTAG) port provided for boundary scan
function
Industrial temperature range: –40 °C to +85 °C
■
■
■
■
■
■
■
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 001-53687 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 10, 2017
CYF0018V
CYF0036V
CYF0072V
Logic Block Diagram
D[35:0]
IE
WEN
WCLK
LD
SPI_SEN SPI_SCLK
INPUT
REGISTER
WRITE
CONTROL LOGIC
CONFIGURATION
REGISTERS/MAILBOX
SPI_SI
MB
FF
PAF
WRITE POINTER
Memory Array
MRS
PRS
FLAG LOGIC
EF
PAE
DVal
HF
RESET POINTER
18 Mbit
36 Mbit
72 Mbit
READ POINTER
TCK
TMS
TDO
TDI
JTAG CONTROL
READ CONTROL
LOGIC
OUTPUT
REGISTER
MARK, RT
RCLK
REN
OE
MEMORY LOGIC
ORGANIZATION
Q[35:0]
PORTSZ[2:0]
Document Number: 001-53687 Rev. *S
Page 2 of 35
CYF0018V
CYF0036V
CYF0072V
Contents
Pin Diagram for CYF0XXXVXXL [1] ................................. 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Selecting Word Sizes .................................................. 7
Memory Organization
for Different Port Sizes ................................................ 7
Data Valid Signal (DVal) .............................................. 8
Write Mask and Read Skip Operation ......................... 8
Flow-through Mailbox Register .................................... 8
Flag Operation ............................................................. 8
Retransmit from Mark Operation ................................. 9
Programming Flag Offsets
and Configuration Registers ........................................ 9
Width Expansion Configuration ................................. 13
Power Up ................................................................... 13
Read/Write Clock Requirements ............................... 13
JTAG Operation ........................................................ 14
Test Access Port ....................................................... 14
Tap Registers ............................................................ 14
JTAG ID Codes ......................................................... 15
OPCODES Supported ............................................... 15
JTAG Instructions ...................................................... 15
Instruction Update and Bypass ................................. 15
TAP Controller State Diagram ................................... 15
Maximum Ratings ........................................................... 16
Operating Range ............................................................. 16
Recommended DC Operating Conditions .................... 16
Electrical Characteristics ............................................... 16
I/O Characteristics .......................................................... 17
Latency Table .................................................................. 17
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagram ............................................................ 30
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Document Number: 001-53687 Rev. *S
Page 3 of 35
CYF0018V
CYF0036V
CYF0072V
Pin Diagram for CYF0XXXVXXL
[1]
Figure 1. 209-ball FBGA pinout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
FF
EF
D4
D6
D8
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
PAF
TDO
2
D0
D2
D5
D7
D9
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
PAE
HF
3
D1
D3
WEN
V
SS
V
CC2
V
SS
V
CC2
V
SS
V
CC2
WCLK
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
D30
D32
D34
4
DNU
DNU
DNU
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CC1
D31
D33
D35
5
PORTSZ0
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
CC1
PRS
DNU
TDI
6
PORTSZ1
PORTSZ2
DNU
LD
V
CCIO
DNU
V
CC1
V
CC1
V
CC1
IE
V
CC1
V
CC1
V
CC1
SPI_SEN
V
CCIO
SPI_SI
DNU
[2]
MRS
DNU
7
DNU
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
CC1
SPI_SCLK
MB
TMS
8
DNU
DNU
DNU
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CC1
V
REF
DNU
TCK
9
RT
REN
RCLK
Vss
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CCIO
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
OE
MARK
DNU
10
Q0
Q2
Q4
Q6
Q8
Q10
Q12
Q14
Q16
V
CCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
11
Q1
Q3
Q5
Q7
Q9
Q11
Q13
Q15
Q17
V
CCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
Notes
1. Pin Diagram for 18-Mbit, 36-Mbit & 72-Mbit; 1.8V & 3.3V IO voltage options.
2. This pin should be tied to V
SS
preferably or can be left floating to ensure normal operation.
Document Number: 001-53687 Rev. *S
Page 4 of 35
CYF0018V
CYF0036V
CYF0072V
Pin Definitions
Pin Name
MRS
PRS
PORTSZ [2:0]
WCLK
LD
WEN
IE
I/O
Input
Input
Input
Input
Input
Input
Input
Pin Description
Master reset: MRS initializes the internal read and write pointers to zero, resets all flags and sets the
output register to all zeroes. During Master Reset, the configuration registers are set to default values.
Partial reset: PRS initializes the internal read and write pointers to zero, resets all flags and sets the
output register to all zeroes. During Partial Reset, the configuration register settings are retained.
Port word size select: Port word width select pins (common for read and write ports).
Write clock: The rising edge clocks data into the FIFO when writes are enabled (WEN asserted). Data
is written into the FIFO memory when LD is high and into configuration registers when LD is low.
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO memory.
Write enable: Control signal to enable writes to the device. When WEN is low data present on the inputs
is written to the FIFO memory or configuration registers on every rising edge of WCLK.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for 'write masking' or incrementing the write pointer without writing into a location.
Data inputs: Data inputs for a 36-bit bus.
Read clock: The rising edge initiates a read from the FIFO when reads are enabled (REN asserted).
Data is read from the FIFO memory when LD is high & from the configuration registers if LD is low.
Read enable: Control signal to enable reads from the device. When REN is low data is read from the
FIFO memory or configuration registers on every rising edge of RCLK.
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Data outputs: Data outputs for a 36-bit bus.
Data valid: Active low data valid signal to indicate valid data on Q[35:0].
Mark for retransmit: When this pin is asserted the memory location corresponding to the data present
on the output bus is marked. Any subsequent retransmit operation resets the read pointer to this location.
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read until the FIFO is empty.
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK.
Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchronized to WCLK.
Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
Serial input: Serial input data in SPI mode.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Test clock (TCK) pin for JTAG.
Test mode select (TMS) pin for JTAG.
Page 5 of 35
D[35:0]
RCLK
REN
OE
Q[35:0]
DVal
MARK
RT
Input
Input
Input
Input
Output
Output
Input
Input
MB
EF
PAE
HF
PAF
FF
SPI_SCLK
SPI_SI
SPI_SEN
TCK
TMS
Input
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Document Number: 001-53687 Rev. *S
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
