CY8C20234, CY8C20334
CY8C20434, CY8C20534
PSoC
®
Programmable System-0n-Chip™
Features
■
Low Power CapSense™ Block
❐
Configurable Capacitive Sensing Elements
❐
Supports Combination of CapSense Buttons, Sliders, Touch-
pads, and Proximity Sensors
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds Running up to 12 MHz
❐
Low Power at High Speed
❐
2.4V to 5.25V Operating Voltage
❐
Industrial Temperature Range: -40°C to +85°C
Flexible On-Chip Memory
❐
8K Flash Program Storage
50,000 Erase/Write Cycles
❐
512 Bytes SRAM Data Storage
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
Interrupt Controller
❐
In-System Serial Programming (ISSP)
Complete Development Tools
❐
Free Development Tool (PSoC Designer™)
❐
Full Featured, In-Circuit Emulator, and
Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
Precision, Programmable Clocking
❐
Internal ±5.0% 6/12 MHz Main Oscillator
❐
Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep
Programmable Pin Configurations
❐
Pull Up, High Z, Open Drain, and CMOS Drive Modes on All
GPIO
❐
Up to 28 Analog Inputs on GPIO
❐
Configurable Inputs on All GPIO
❐
Selectable, Regulated Digital I/O on Port 1
• 3.0V, 20 mA Total Port 1 Source Current
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux
❐
Common Internal Analog Bus
❐
Simultaneous Connection of I/O Combinations
❐
Comparator Noise Immunity
❐
Low Dropout Voltage Regulator for the Analog Array
■
■
Additional System Resources
❐
Configurable Communication Speeds
• I
2
C: Selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: Configurable between 46.9 kHz and 3 MHz
2
❐
I C Slave
❐
SPI Master and SPI Slave
❐
Watchdog and Sleep Timers
❐
Internal Voltage Reference
❐
Integrated Supervisory Circuit
■
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Config LDO
PSoC
CORE
System Bus
■
Global Analog Interconnect
SRAM
512 Bytes
Interrupt
Controller
SROM
Flash 8K
Sleep and
Watchdog
CPU Core
(M8C)
6/12 MHz Internal Main Oscillator
■
■
ANALOG
SYSTEM
CapSense
Block
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 16, 2009
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PSoC
®
Functional Overview
The
PSoCfamily
consists
of
many
Programmable
System-on-Chips with On-Chip Controller
devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 1,
consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.
Figure 1. Analog System Block Diagram
ID AC
Analog Global Bus
Vr
R eferenc e
Buffer
C internal
C om parator
Mux
Mux
R efs
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO (Internal
Main Oscillator), and ILO (Internal Low speed Oscillator). The
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture
microprocessor.
System Resources provide additional capability such as a
configurable I
2
C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The Analog System consists of the CapSense PSoC block and
an internal 1.8V analog reference. Together they support capac-
itive sensing of up to 28 inputs.
C ap Sens e C ounters
C SC LK
IMO
C apSens e
C lock Selec t
R elaxation
O s c illator
(RO)
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Complex capacitive sensing interfaces such as sliders and
touch pads
Chip-wide mux that enables analog input from any I/O pin
Crosspoint connection between any I/O pin combinations
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, found under
http://www.cypress.com
>> DESIGN
RESOURCES >> Application Notes. In general, unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) requirement for CapSense
applications is 5:1.
Document Number: 001-05356 Rev. *H
Page 2 of 34
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Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource are presented below.
■
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc.
Select Application Notes under the
Documentation tab.
The I
2
C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
An internal 1.8V reference provides an absolute reference for
capacitive sensing.
The 5V maximum input, 3V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop
and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
■
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at
www.cypress.com/training.
The
training covers a wide variety of topics and skill levels to assist
you in your designs.
■
■
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
www.cypress.com/cypros.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming infor-
mation, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at
www.cypress.com/psoc.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 001-05356 Rev. *H
Page 3 of 34
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Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers.
The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers.
C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 001-05356 Rev. *H
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I
2
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-05356 Rev. *H
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