CY7C68053
MoBL-USB™ FX2LP18 USB
Microcontroller
1. CY7C68053 Features
■
■
■
USB 2.0 – USB-IF High Speed and Full Speed Compliant
(TID# 40000188)
Single-Chip Integrated USB 2.0 Transceiver, Smart SIE,
and Enhanced 8051 Microprocessor
Ideal for Mobile Applications (Cell Phone, Smart Phones,
PDAs, MP3 Players)
❐
Ultra low power
❐
Suspend current: 20 µA (typical)
Software: 8051 Code runs from:
❐
Internal RAM, which is loaded from EEPROM
16 kBytes of On-Chip Code/Data RAM
Four Programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐
Buffering options: double, triple, and quad
Additional Programmable (BULK/INTERRUPT) 64-Byte
Endpoint
8 or 16-Bit External Data Interface
Smart Media Standard ECC Generation
GPIF (General Programmable Interface)
❐
Allows direct connection to most parallel interface
❐
Programmable waveform descriptors and configuration
registers to define waveforms
❐
Supports multiple Ready and Control outputs
■
Integrated, Industry Standard Enhanced 8051
❐
48 MHz, 24 MHz, or 12 MHz CPU operation
❐
Four clocks per instruction cycle
❐
Three counter/timers
❐
Expanded interrupt system
❐
Two data pointers
1.8V Core Operation
1.8V to 3.3V I/O Operation
Vectored USB Interrupts and GPIF/FIFO Interrupts
Separate Data Buffers for Setup and Data Portions of a
CONTROL Transfer
Integrated I
2
C Controller, runs at 100 or 400 kHz
Four Integrated FIFOs
❐
Integrated glue logic and FIFOs lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
Uses external clock or asynchronous strobes
❐
Easy interface to ASIC and DSP ICs
Available in Industrial Temperature Grade
Available in one Pb-free Package with up to 24 GPIOs
❐
56-pin VFBGA (24 GPIOs)
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Block Diagram
24 MHz
Ext. XTAL
High-performance microprocessor
using standard tools
with lower-power options
MoBL-USB FX2LP18
VCC
12/24/48 MHz,
Four Clocks/Cycle
A dd re ss ( 16) / D ata Bu s (8)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
I C
Master
Additional IOs (24)
2
1.5K
Connected for
Full-Speed
D+
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Abundant IO
GPIF
ECC
RDY (2)
CTL (3)
D–
Integrated
Full- and High-Speed
XCVR
General
Programmable I/F
To Baseband Processors/
Application Processors/
ASICS/DSPs
Up to 96 MBytes/sec
Burst Rate
4 KB
FIFO
8/16
Enhanced USB Core
Simplifies 8051 Code
“Soft Configuration”
Easy Firmware Changes
FIFO and Endpoint Memory
(Master or Slave Operation)
Cypress Semiconductor Corporation
Document # 001-06120 Rev *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 02, 2009
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CY7C68053
Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18
(CY7C68053) is a low voltage (1.8V) version of the EZ-USB
®
FX2LP (CY7C68013A), which is a highly integrated, low power
USB 2.0 microcontroller. By integrating the USB 2.0 transceiver,
serial interface engine (SIE), enhanced 8051 microcontroller,
and a programmable peripheral interface in a single chip,
Cypress has created a very cost effective solution that provides
superior time-to-market advantages with low power to enable
bus powered applications.
The ingenious architecture of MoBL-USB FX2LP18 results in
data transfer rates of over 53 Mbytes per second, the maximum
allowable USB 2.0 bandwidth, while still using a low cost 8051
microcontroller in a package as small as a 56VFBGA (5 mm x
5 mm). Because it incorporates the USB 2.0 transceiver, the
MoBL-USB FX2LP18 is more economical, providing a smaller
footprint solution than USB 2.0 SIE or external transceiver
implementations. With MoBL-USB FX2LP18, the Cypress Smart
SIE handles most of the USB 1.1 and 2.0 protocol in hardware,
freeing the embedded microcontroller for application-specific
functions and decreasing development time to ensure USB
compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The MoBL-USB FX2LP18 is also referred to as FX2LP18 in this
document.
3.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP18 family has
256 bytes of register RAM, an expanded interrupt system, and
three timer/counters.
3.2.1 8051 Clock Frequency
FX2LP18 has an on-chip oscillator circuit that uses an external
24 MHz (±100-ppm) crystal with the following characteristics:
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■
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Parallel resonant
Fundamental mode
500 µW drive level
12 pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY; internal counters divide it
down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Figure 1. Crystal Configuration
24 MHz
C1
12 pF
C2
12 pF
2. Applications
There are a wide variety of applications for the MoBL-USB
FX2LP18. It is used in cell phones, smart phones, PDAs, and
MP3 players, to name a few.
The ‘Reference Designs’ section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. For more
information, visit
http://www.cypress.com.
20 × PLL
12 pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
The CLKOUT pin, which can be tristated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency — 48, 24, or 12 MHz.
3.2.2 Special Function Registers
Certain 8051 Special Function Register (SFR) addresses are
populated to provide fast access to critical FX2LP18 functions.
These SFR additions are shown in
Table 1
on page 3. Bold type
indicates non standard, enhanced 8051 registers. The two SFR
rows that end with ‘0’ and ‘8’ contain bit-addressable registers.
The four I/O ports A–D use the SFR addresses used in the
standard 8051 for ports 0–3, which are not implemented in
FX2LP18. Because of the faster and more efficient SFR
addressing, the FX2LP18 I/O ports are not addressable in
external RAM space (using the MOVX instruction).
3. Functional Overview
The functionality of this chip is described in the sections below.
3.1 USB Signaling Speed
FX2LP18 operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000.
■
■
Full speed, with a signaling bit rate of 12 Mbps
High speed, with a signaling bit rate of 480 Mbps
FX2LP18 does not support the low speed signaling mode of
1.5 Mbps.
Document # 001-06120 Rev *I
Page 2 of 40
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CY7C68053
Table 1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
SCON0
SBUF0
AUTOPTRH1
AUTOPTRL1
Reserved
AUTOPTRH2
AUTOPTRL2
Reserved
AUTOPTRSET-UP
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATLNOX
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware does.
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TH2
IE
IP
T2CON
EICON
EIE
EIP
9x
IOB
EXIF
MPAGE
Ax
IOC
INT2CLR
Bx
IOD
IOE
OEA
OEB
OEC
OED
OEE
Cx
SCON1
SBUF1
Dx
PSW
Ex
ACC
Fx
B
3.3 I
2
C™ Bus
FX2LP18 supports the I
2
C bus as a master only at
100 or 400 KHz. SCL and SDA pins have open-drain outputs
and hysteresis inputs. These signals must be pulled up to either
V
CC
or V
CC_IO
, even if no I
2
C device is connected. (Connecting
to V
CC_IO
may be more convenient.)
3.4 Buses
This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional data
bus, multiplexed on I/O ports B and D.
3.7 Bus-Powered Applications
The FX2LP18 fully supports bus-powered designs by
enumerating with less than 100 mA as required by the USB 2.0
specification.
3.5 USB Boot Methods
During the power up sequence, internal logic checks the I
2
C port
for the connection of an EEPROM whose first byte is 0xC2. If
found, it boot-loads the EEPROM contents into internal RAM
(0xC2 load). If no EEPROM is present, an external processor
must emulate an I
2
C slave. The FX2LP18 does not enumerate
using internally stored descriptors (for example, Cypress’s
VID/PID/DID is not used for enumeration).
[1]
3.8 Interrupt System
The FX2LP18 interrupts are described in this section.
3.8.1 INT2 Interrupt Request and Enable Registers
FX2LP18 implements an autovector feature for INT2. There are
27 INT2 (USB) vectors. See the
MoBL-USB™ Technical
Reference Manual (TRM)
for more details.
3.8.2 USB Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is normally required to
identify the individual USB interrupt source, the FX2LP18
provides a second level of interrupt vectoring, called
‘Autovectoring.’ When a USB interrupt is asserted, the FX2LP18
pushes the program counter onto its stack then jumps to address
0x0043, where it expects to find a ‘jump’ instruction to the USB
interrupt service routine.
The FX2LP18 jump instruction is encoded as shown in
Table 2
on page 4.
3.6 ReNumeration™
Because the FX2LP18’s configuration is soft, one chip can take
on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP18 enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP18 enumerates
again, this time as a device defined by the downloaded
information. This patented two-step process, called
ReNumeration™, happens instantly when the device is plugged
in, with no hint that the initial download step has occurred.
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
Note
1. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document # 001-06120 Rev *I
Page 3 of 40
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CY7C68053
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP
register), the FX2LP18 substitutes its INT2VEC byte. Therefore,
if the high byte (‘page’) of a jump-table address is preloaded at
Table 2. INT2 USB Interrupts
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
INT2VEC Value
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP4
EP6
EP8
IBN
SUDAV
SOF
SUTOK
SUSPEND
USB RESET
HISPEED
EP0ACK
Source
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
Notes
Setup data available
Start of frame (or microframe)
Setup token received
USB suspend request
Bus reset
Entered high speed operation
FX2LP18 ACK’d the control handshake
Reserved
EP0-IN ready to be loaded with data
EP0-OUT has USB data
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
Reserved
EP0 OUT was pinged and it NAK’d
EP1 OUT was pinged and it NAK’d
EP2 OUT was pinged and it NAK’d
EP4 OUT was pinged and it NAK’d
EP6 OUT was pinged and it NAK’d
EP8 OUT was pinged and it NAK’d
Bus errors exceeded the programmed limit
Reserved
Reserved
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
Document # 001-06120 Rev *I
Page 4 of 40
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CY7C68053
Figure 2. Reset Timing Plots
RESET#
RESET#
V
IL
1.8V
1.62V
V
CC
0V
T
RESET
Power on Reset
V
IL
1.8V
V
CC
0V
T
RESET
Powered Reset
3.9 Reset and Wakeup
The reset and wakeup pins are described in detail in this section.
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP18 when asserted.
This pin has hysteresis and is active LOW. When a crystal is
used with the CY7C68053, the reset period must allow for the
stabilization of the crystal and the PLL. This reset period must be
approximately 5 ms after VCC has reached 3.0V. If the crystal
input pin is driven by a clock signal the internal PLL stabilizes in
200
μs
after V
CC
has reached 3.0V
[2]
.
Figure 2
shows a power
on reset condition and a reset applied during operation. A power
on reset is defined as the time reset is asserted while power is
being applied to the circuit. A powered reset is defined as a reset
in which the FX2LP18 has previously been powered on and
operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation, which can be
found on the Cypress web site. For more information on reset
implementation for the MoBL-USB family of products, visit the
Cypress web site at
http://www.cypress.com.
Table 3. Reset Timing Values
Condition
Power on reset with crystal
Power on reset with external
clock
Powered reset
3.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
wakeup interrupt. This applies whether or not FX2LP18 is
connected to the USB.
T
RESET
5 ms
200
μs
+ clock stability time
200
μs
The FX2LP18 exits the power down (USB suspend) state using
one of the following methods:
■
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP18 and initiate a
wakeup)
External logic asserts the WAKEUP pin
External logic asserts the PA3/WU2 pin
■
■
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is active LOW by default.
3.9.3 Lowering Suspend Current
Good design practices for CMOS circuits dictate that any unused
input pins must not be floating between V
IL
and V
IH
. Floating
input pins will not damage the chip, but can substantially
increase suspend current. To achieve the lowest suspend
current, confiigure unused port pins as outputs. Connect unused
input pins to ground. Some examples of pins that need attention
during suspend are:
■
Port pins. For Port A, B, D pins, take extra care in shared bus
situations.
❐
Connect completely unused pins to V
CC_IO
or GND.
❐
In a single-master system, the firmware must output enable
all the port pins and drive them high or low, before FX2LP18
enters the suspend state.
❐
In a multi-master system (FX2LP18 and another processor
sharing a common data bus), when FX2LP18 is suspended,
the external master must drive the pins high or low. The
external master must not let the pins float.
CLKOUT. If CLKOUT is not used, it must be tri-stated during
normal operation, but driven during suspend.
IFCLK, RDY0, RDY1. These pins must be pulled to V
CC_IO
or
GND or driven by another chip.
■
■
Note
2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200
μs.
Document # 001-06120 Rev *I
Page 5 of 40
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