which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or
Little Endian configurations.
The CY7C436X4 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X4 have two modes of operation. In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long-word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First- Word Fall-Through mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
[1]
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state.”
[2]
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB can be
loaded in parallel using Port A or in serial via the SD input.
Three default offset settings are also provided. The AEA and
AEB threshold can be set at 8, 16, or 64 locations from the
empty boundary and AFA and AFB threshold can be set at 8,
16, or 64 locations from the full boundary. All these choices are
made using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
Retransmit feature is available on these devices.
The CY7C436X4 are characterized for operation from 0
°
C to
70
°C commercial, and from –40°
C to 85
°C industrial
. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Pin Definitions
Signal Name
A
0–35
AEA
Description
Port A Data
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
I/O
O
Function
Programmable Almost Empty flag synchronized to CLKA.
It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.
[2]
Programmable Almost Empty flag synchronized to CLKB.
It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.
[2]
Programmable Almost Full flag synchronized to CLKA.
It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
[2]
Programmable Almost Full flag synchronized to CLKB.
It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
[2]
I/O
36-bit bidirectional data port for side A.
AEB
O
AFA
O
AFB
O
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer
to “Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06022 Rev. *B
Page 3 of 39
CY7C43644
CY7C43664
CY7C43684
Pin Definitions
(continued)
Signal Name
B
0–35
BE/FWFT
Description
Port B Data
Big
Endian/First-
Word Fall-
Through
Select
I/O
I
Function
This is a dual-purpose pin.
During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port B to
Port A the first word/byte written to Port B will come out as the most significant word/byte
on Port A. A LOW on BE will select Little Endian operation. In this case, the least signif-
icant byte or word on Port A is transferred to Port B first for A-to-B data flow. Similarly,
the fist word/byte written into Port B will come out as the least significant word/byte on
Port A for B-to-A data flow. After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode.
Once the timing mode has been selected, the level on this pin must be static throughout
device operation.
A
HIGH on this pin enables either byte or word bus width on Port B,
depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A
and
can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B
and
can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA
to read or write on
Port A. The A
0–35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB
to read or write on
Port B. The B
0–35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0–35
outputs, available
for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
[1]
This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
0–35
outputs, available
for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
[1]
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA
to read or write data
on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB
to read or write data
on Port B.
This is a dual-function pin.
In the CY Standard mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual-function pin.
In the CY Standard mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
I/O
36-bit bidirectional data port for side B.
BM
Bus Match
Select (Port
A)
Port A Clock
I
CLKA
I
CLKB
Port B Clock
I
CSA
CSB
EFA/ORA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A
Full/Input
Ready Flag
Port B
Full/Input
Ready Flag
I
I
O
EFB/ORB
O
ENA
ENB
FFA/IRA
I
I
O
FFB/IRB
O
Document #: 38-06022 Rev. *B
Page 4 of 39
CY7C43644
CY7C43664
CY7C43684
Pin Definitions
(continued)
Signal Name
FS1/SEN
Description
Flag Offset
Select
1/Serial
Enable
Flag Offset
Select
0/Serial Data
I/O
I
Function
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming.
During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, or serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the
X and Y registers. The number of bit writes required to program the offset registers is 40
for the CY7C43644, 48 for the CY7C43664, and 56 for the CY7C43684. The first bit write
stores the Y-register MSB and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write
operation.
When a read operation is performed on Port A, a HIGH level on MBA selects
data from the Mail2 register for output and a LOW level selects FIFO2 output register data
for output. When a write operation is performed on Port A, a HIGH level on MBA will write
the data into Mail 1 register. While a LOW level will write the data into FIFO1.
A HIGH level on MBB chooses a mailbox register for a Port B read or write
operation.
When a read operation is performed on Port B, a HIGH level on MBB selects
data from the Mail1 register for output and a LOW level selects FIFO1 output register data
for output. When a write operation is performed on Port B, a HIGH level on MBB will write
the data into Mail 2 register, while a LOW level will write the data into FIFO2.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register.
Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register.
Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers
to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers
to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions
of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
A LOW on this pin initializes the FIFO1 read and write pointers
to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or parallel),
and programmable flag settings are all retained.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. During
Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
A LOW strobe on this pin will retransmit the data on FIFO1.
This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operations to retransmit the data. Retransmit function applies to CY standard mode only.
A LOW strobe on this pin will retransmit data on FIFO2.
This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B.
A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE
to select the bus size and endian arrangement for Port B. The level of SIZE must be static
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