CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64 x 18 (CY7C4425V)
• 256 x 18 (CY7C4205V)
• 512 x 18 (CY7C4215V)
• 1K x 18 (CY7C4225V)
• 2K x 18 (CY7C4235V)
• 4K x 18 (CY7C4245V)
• 0.65µ CMOS
• High-speed 67-MHz operation (15-ns read/write cycle
times)
• Low power
— I
CC
= 30 mA
• 5V tolerant inputs (V
IH MAX
= 5V)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Depth-Expansion Capability
• 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP
• Pb-Free packages available
Functional Description
The CY7C42X5V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide. The CY7C42X5V can be cascaded to
increase FIFO depth. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a Free-Running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C42X5V have an Output Enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 66 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI and RXI pins of the
first device. The FL pin of the first device is tied to V
SS
and the
FL pin of all the remaining devices should be tied to V
CC
.
The CY7C42X5V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see
Table 2).
The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the write
clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. As mentioned previously, the
Almost Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to V
SS
. All configurations are fabricated
using an advanced 0.65µ P-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Cypress Semiconductor Corporation
Document #: 38-06029 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 7, 2005
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Logic Block Diagram
D
0–17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
RAM
ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
OE
Q
0–17
READ
CONTROL
RCLK
REN
Pin Configuration
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
/SMODE
STQFP/TQFP
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D
16
D
17
GND
RCLK
FL/RT
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
PAE
Q
0
Q
1
GND
Q
2
Document #: 38-06029 Rev. *C
Q
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4425V
CY7C4205V
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
Page 2 of 20
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Selection Guide
CY7C42X5V-15
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Operating Current
CY7C4425V
Density
Packages
64 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Commercial
CY7C4205V
256 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
66.7
11
15
4
1
11
30
CY7C4215V
512 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C42X5V-25
40
15
25
6
1
15
30
CY7C4225V
1K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C42X5V-35
28.6
20
35
7
2
20
30
CY7C4235V
2K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Unit
MHz
ns
ns
ns
ns
ns
mA
CY7C4245V
4K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Pin Definitions
Signal Name
D
0−17
Q
0−17
WEN
REN
WCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I/O
I
O
I
I
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full.
When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty.
When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
Dual-Mode Pin.
Single device or width expansion - Half Full status flag. Cascaded –
Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty.
EF is synchronized to RCLK.
When FF is LOW, the FIFO is full.
FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty
offset value programmed into the FIFO.
PAE is asynchronous when
V
CC
/SMODE is tied to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied
to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset
value programmed into the FIFO.
PAF is asynchronous when V
CC
/SMODE is
tied to V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0−17
(O
0−17
) are written (read) into (from) the program-
mable-flag-offset register.
Dual-Mode Pin.
Cascaded – The first device in the daisy chain will have FL tied to
V
SS
; all other devices will have FL tied to V
CC
. In standard mode of width
expansion, FL is tied to V
SS
on all devices. Not Cascaded – Tied to V
SS
. Retransmit
function is also available in standalone mode by strobing RT.
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
SS
.
Function
RCLK
Read Clock
I
WXO/HF
EF
FF
PAE
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
O
O
O
O
PAF
Programmable
Almost Full
Load
First Load/
Retransmit
O
LD
FL/RT
I
I
WXI
RXI
Write Expansion
Input
Read Expansion
Input
I
I
Document #: 38-06029 Rev. *C
Page 3 of 20
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Pin Definitions
(continued)
Signal Name
RXO
RS
OE
Description
Read Expansion
Output
Reset
Output Enable
I/O
O
I
I
Function
Cascaded – Connected to RXI of next device.
Resets device to empty condition.
A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
Dual-Mode Pin.
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
. (Almost Empty
synchronized to RCLK, Almost Full synchronized to WCLK.)
V
CC
/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Architecture
The CY7C42X5V consists of an array of 64 to 4K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C42X5V also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
Programming
The CY7C42X5V devices contain two 12-bit offset registers.
Data present on D
0–11
during a program write will determine
the distance from Empty (Full) that the Almost Empty (Almost
Full) flags become active. If the user elects not to program the
FIFO’s flags, the default offset values are used (see
Table 2).
When the Load LD pin is set LOW and WEN is set LOW, data
on the inputs D
0–11
is written into the Empty offset register on
the first LOW-to-HIGH transition of the write clock (WCLK).
When the LD pin and WEN are held LOW then data is written
into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see
Table 1).
Writing all offset registers does not have to
occur at one time. One or two offset registers can be written
and then, by bringing the LD pin HIGH, the FIFO is returned to
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
LD
0
WEN
0
WCLK
[1]
Selection
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, a falling edge must occur on RS
and the user must not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the
D
0-17
pins is written into the FIFO on each rising edge of the
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q
0−17
outputs. New data will be presented on each rising edge of
RCLK while REN is active LOW and OE is LOW. REN must
set up t
ENS
before RCLK for it to be a valid read function. WEN
must occur t
ENS
before WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
0−17
outputs
after t
OE
. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0−17
outputs
even after additional reads occur.
0
1
1
0
Write Into FIFO
1
1
No Operation
Note:
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06029 Rev. *C
Page 4 of 20
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Flag Operation
The CY7C42X5V devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if V
CC
/SMODE
is tied to V
SS
.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5V features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
Table 2. Flag Truth Table
Number of Words in FIFO
7C4425V - 64 x 18
0
1 to n
[2]
(n + 1) to 32
33 to (64
−
(m + 1))
(64
−
m)
[3]
to 63
64
0
1 to n
[2]
(n + 1) to 128
129 to (256
−
(m + 1))
(256
−
m)
[3]
to 255
256
Number of Words in FIFO
7C4225V - 1K x 18
0
1 to n
[2]
(n + 1) to 512
513 to (1024
−
(m + 1))
(1024
−
1024
m)
[3]
to 1023
0
1 to n
[2]
(n + 1) to 1024
1025 to (2048
−
(m + 1))
(2048
−
2048
m)
[3]
to 2047
7C4235V - 2K x 18
0
1 to n
[2]
(n + 1) to 2048
2049 to (4096
−
(m + 1))
(4096
−
4096
m)
[3]
to 4095
7C4245V - 4K x 18
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
7C4205V - 256 x 18
0
1 to n
[2]
(n + 1) to 256
257 to (512
−
(m + 1))
(512
−
m)
[3]
to 511
512
7C4215V - 512 x 18
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
that the FIFO is either Almost Full or Almost Empty. See
Table 2
for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal
transition is caused by the rising edge of the write clock and
the PAE flag transition is caused by the rising edge of the read
clock.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location
of the FIFO. WCLK and RCLK may be free running but must
be disabled during and tRTR after the retransmit pulse. With
every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal
to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during
a retransmit cycle. Data written to the FIFO after activation of
RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Note:
2. n = Empty Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
3. m = Full Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
Document #: 38-06029 Rev. *C
Page 5 of 20
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