CY7C421512 × 9 Asynchronous FIFO
CY7C421
512 × 9 Asynchronous FIFO
512 × 9 Asynchronous FIFO
Features
■
Functional Description
The CY7C421 is a first-in first-out (FIFO) memory offered in
300-mil wide SOJ, TQFP & PLCC packages and it is 512 words
by 9 bits wide. Each FIFO memory is organized such that the
data is read in the same sequential order that it was written. Full
and empty flags are provided to prevent overflow and underflow.
Three additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to another
in parallel. This eliminates the serial addition of propagation
delays, so that throughput is not reduced. Data is steered in a
similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFO to retransmit the data.
Read enable (R) and write enable (W) must both be HIGH during
retransmit, and then R is used to access the data.
The CY7C421 is fabricated using an advanced 0.65-micron
P-well CMOS technology. Input ESD protection is greater than
2000 V and latch up is prevented by careful layout and guard
rings.
For a complete list of related documentation,
click here.
Asynchronous First-In First-Out (FIFO) Buffer Memories
❐
512 × 9 (CY7C421)
Dual-Ported RAM Cell
High Speed 50 MHz Read and Write Independent of Depth and
Width
Low Operating Power: I
CC
= 35 mA
Empty and Full Flags (Half Full Flag in Standalone)
TTL Compatible
Retransmit in Standalone
Expandable in Width
PLCC, 7 × 7 TQFP, 300-Mil Molded SOJ
Pb-free Packages Available
Pin Compatible and Functionally Equivalent to IDT7201, and
AM7201
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Selection Guide
512 × 9
Frequency (MHz)
Maximum Access Time (ns)
I
CC1
(mA)
-15
40
15
35
-20
33.3
20
35
Cypress Semiconductor Corporation
Document Number: 38-06001 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 14, 2016
CY7C421
Logic Block Diagram
DATA INPUTS
(D0–D 8)
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
512 x 9
READ
POINTER
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0–Q 8)
R
READ
CONTROL
FLAG
LOGIC
RESET
LOGIC
MR
FL/RT
EF
FF
XI
EXPANSION
LOGIC
XO/HF
Document Number: 38-06001 Rev. *K
Page 2 of 22
CY7C421
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics ................................................. 6
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Architecture .................................................................... 13
Dual-Port RAM .......................................................... 13
Resetting the FIFO .................................................... 13
Writing Data to the FIFO ........................................... 13
Reading Data from the FIFO ..................................... 13
Standalone/Width Expansion Modes ........................ 13
Depth Expansion Mode ............................................. 13
Use of the Empty and Full Flags ............................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 38-06001 Rev. *K
Page 3 of 22
CY7C421
Pin Configurations
Figure 1. 32-pin PLCC/LCC (Top View)
Figure 2. 28-pin DIP (Top View)
Figure 3. 32-pIn TQFP (Top View)
D
3
D
8
W
V
CC
D
4
D
2
D
5
D
6
D
3
D
8
W
NC
V
cc
D
4
D
5
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
4 3 2 1 323130
5
29
6
28
7
27
8
26
7C421
9
25
10
24
11
23
12
22
13
21
14 15 1617 181920
Q
3
Q
8
GND
NC
R
Q
4
Q
5
D
6
D
7
NC
FL/RT
MR
EF
XO/HF
Q
7
Q
6
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
7C421
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D
4
D
5
D
6
D
7
FL/RT
MR
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
32 3130 29 28 27 26 25
D
1
D
0
NC
NC
XI
FF
Q
0
Q
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D
7
FL/RT
NC
NC
MR
EF
XO/HF
Q
7
7C421
9 10 11 12 13 14 15 16
Q
2
Q
3
Q
8
GND
R
Q
4
Q
5
Document Number: 38-06001 Rev. *K
Q
6
Page 4 of 22
CY7C421
Pin Definitions
Signal Name
W
R
D
0
–D
8
Q
0
–Q
8
XI
XO
HF
FF
EF
MR
RT
FL
Description
Write Signal
Read Signal
Input Data
Output Data
Expansion In
Expansion Out
Half Full Flag
Full Flag
Empty Flag
Master Reset
Retransmit
First Load
I/O
I
I
I
I
Write into the FIFO
Read from the FIFO
Data into the FIFO
Cascaded: Connected to XO of pervious device
Non-Cascaded: Connected to V
CC
Function
O Data Out from the FIFO
O Cascaded: Connected to XI of next device
Non-Cascaded: Connected to V
CC
O Half-full flag: When HF is LOW, half of the FIFO is full.
O When FF is LOW, the FIFO is full.
O When EF is LOW, the FIFO is empty.
I
I
I
FIFO Reset
Causes FIFO to retransmit the data
Width expansion: Connected to V
CC
Depth expansion: when Gnd indicates that part is first to be loaded all others connected to
V
CC
Voltage Supply
Ground
V
CC
GND
Power
Ground
I
I
Document Number: 38-06001 Rev. *K
Page 5 of 22
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