The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE
1
or CE
2
), reducing the power
consumption when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
I/O
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
256 x 32 x 8
ARRAY
CE
1
CE
2
WE
OE
COLUMN DECODER
POWER
DOWN
I/O
7
A
10
A
11
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
12
A
0
A
9
Cypress Semiconductor Corporation
Document #: 38-05466 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 10, 2005
PRELIMINARY
Selection Guide
CY7C185D-10
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
10
60
3
CY7C185D-12
12
50
3
CY7C185D
CY7C185D-15
15
40
3
Unit
ns
mA
mA
Document #: 38-05466 Rev. *C
Page 2 of 10
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................... −0.5V
to V
CC
+ 0.5V
CY7C185D
DC Input Voltage
[2]
.................................... −0.5V
to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C185D-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.5
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+1
+1
–300
60
10
3.0
2.0
–0.5
–1
–1
Max.
7C185D-12
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+1
+1
–300
50
10
3.0
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Output Short Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
V
CC
Operating Supply Current V
CC
= Max., I
OUT
= 0 mA
Automatic Power-down Current Max. V
CC
, CE
1
≥
V
IH
or CE
2
≤
V
IL
Min. Duty Cycle = 100%
Automatic Power-down Current Max. V
CC
, CE
1
≥
V
CC
– 0.3V,
or CE
2
≤
0.3V
V
IN
≥
V
CC
– 0.3V or V
IN
≤
0.3V
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
7C185D-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Min.
2.4
0.4
2.0
–0.5
–1
–1
V
CC
+ 0.3V
0.8
+1
+1
–300
40
10
3.0
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Output Short Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
V
CC
Operating Supply Current V
CC
= Max., I
OUT
= 0 mA
Automatic Power-down Current Max. V
CC
, CE
1
≥
V
IH
or CE
2
≤
V
IL
Min. Duty Cycle = 100%
Automatic Power-down Current Max. V
CC
, CE
1
≥
V
CC
– 0.3V or CE
2
≤
0.3V
V
IN
≥
V
CC
– 0.3V or V
IN
≤
0.3V
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
7
Unit
pF
pF
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05466 Rev. *C
Page 3 of 10
PRELIMINARY
Thermal Resistance
[4]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[4]
Thermal Resistance
(Junction to Case)
[4]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
CY7C185D
All-Packages
TBD
TBD
Unit
°C/W
°C/W
AC Test Loads and Waveforms
10-ns Device
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50Ω
ALL INPUT PULSES
3.0V
10%
90%
90%
10%
≤
3 ns
High-Z characteristics:
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R1 481
Ω
30 pF*
GND
≤
3 ns
12, 15-ns Devices
R1 481
Ω
5V
OUTPUT
30 pF
1.73V
INCLUDING
JIG AND
SCOPE
R2
255Ω
(a)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
R2
255Ω
(b)
(c)
Switching Characteristics
Over the Operating Range
[6]
7C185D-10
Parameter
Read Cycle
t
power[5]
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7]
CE
1
LOW to Low Z
[8]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[7, 8]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
2
to HIGH to Power-Up
CE
1
HIGH to Power-Down
CE
2
LOW to Power-Down
0
10
3
3
5
0
12
3
5
3
3
6
0
15
3
10
10
5
3
6
3
3
7
100
10
10
3
12
12
6
3
7
100
12
12
3
15
15
8
100
15
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C185D-12
Min.
Max.
7C185D-15
Min.
Max.
Unit
Notes:
5. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±200
mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE1
and t
LZCE2
for any given device.
Document #: 38-05466 Rev. *C
Page 4 of 10
PRELIMINARY
Switching Characteristics
Over the Operating Range (continued)
[6]
7C185D-10
Parameter
Write Cycle
[9]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[7]
WE HIGH to Low Z
3
10
8
8
7
0
0
7
6
0
6
3
12
10
10
10
0
0
10
7
0
6
3
15
12
12
12
0
0
12
8
0
Description
Min.
Max.
7C185D-12
Min.
Max.
CY7C185D
7C185D-15
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR [4]
t
R[10]
Description
V
CC
for Data Retention
Data Retention Current Non-L, Com’l / Ind’l
L-Version Only
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
3
1.2
0
t
RC
Max.
Unit
V
mA
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
DR
>
2V
4.5V
t
R
Switching Waveforms
Read Cycle No.1
[11,12]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes:
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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