CY7C1518KV18
CY7C1520KV18
72-Mbit DDR-II SRAM Two-Word
Burst Architecture
72-Mbit DDR-II SRAM Two-Word Burst Architecture
Features
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Configurations
CY7C1518KV18 – 4M × 18
CY7C1520KV18 – 2M × 36
72-Mbit density (4M × 18, 2M × 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–V
DD
)
❐
Supports both 1.5 V and 1.8 V IO supply
Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible Test Access Port
Phase-locked loop (PLL) for accurate data placement
Functional Description
The CY7C1518KV18, and CY7C1520KV18 are 1.8 V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1518KV18 and CY7C1520KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518KV18 and two 36-bit words in the case of
CY7C1520KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
× 18
× 36
333 MHz
333
520
640
300 MHz
300
490
600
250 MHz
250
430
530
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-00437 Rev. *V
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 6, 2017
CY7C1518KV18
CY7C1520KV18
Logic Block Diagram – CY7C1518KV18
Burst
Logic
A0
A
(21:0)
22
LD
K
K
21
Write Add. Decode
Read Add. Decode
A
(21:1)
Address
Register
Write
Reg
2M x 18 Array
Write
Reg
18
2M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
36
Control
Logic
V
REF
R/W
BWS
[1:0]
18
18
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ
[17:0]
Logic Block Diagram – CY7C1520KV18
A0
Burst
Logic
A
(20:0)
21
LD
K
K
20
Write Add. Decode
Read Add. Decode
A
(20:1)
Address
Register
Write
Reg
1M x 36 Array
Write
Reg
36
1M x 36 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
72
Control
Logic
V
REF
R/W
BWS
[3:0]
36
36
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ
[35:0]
Document Number: 001-00437 Rev. *V
Page 2 of 32
CY7C1518KV18
CY7C1520KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Burst Address Table ........................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in DDR II SRAM ........................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 26
Read/Write/Deselect Sequence ................................ 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-00437 Rev. *V
Page 3 of 32
CY7C1518KV18
CY7C1520KV18
Pin Configurations
The pin configurations for CY7C1518KV18, and CY7C1520KV18 follow.
[1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1518KV18 (4M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1520KV18 (2M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
A
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00437 Rev. *V
Page 4 of 32
CY7C1518KV18
CY7C1520KV18
Pin Definitions
Pin Name
DQ
[x:0]
I/O
Pin Description
Input Output-
Data input output signals.
Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the C and C clocks during read operations or K and K when in single
clock mode. When read access is deselected, Q
[x:0]
are automatically tristated.
CY7C1518KV18
DQ
[17:0]
CY7C1520KV18
DQ
[35:0]
Input-
Synchronous load.
This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.
Input-
Byte Write Select 0, 1, 2, and 3
Active LOW.
Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C1518KV18 BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1520KV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address inputs.
These address inputs are multiplexed for both read and write operations. Internally,
Synchronous the device is organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C1518KV18, and 2M × 36 (2
arrays each of 1M × 36) for CY7C1520KV18.
CY7C1518KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 22 address inputs are needed to access the entire memory array.
CY7C1520KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 21 address inputs are needed to access the entire memory array. All the address inputs are
ignored when the appropriate port is deselected.
Input-
Synchronous read or write input.
When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Input Clock
Positive input clock for output data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
Negative input clock for output data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
Positive input clock input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative input clock input.
K is used to capture synchronous data being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
LD
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A, A
0
R/W
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Output Clock
CQ referenced with respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Clock
CQ referenced with respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Input
Output impedance matching input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
CQ
ZQ
Document Number: 001-00437 Rev. *V
Page 5 of 32
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