CY7C1444AV33
CY7C1445AV33
36-Mbit (1M x 36/2Mx 18) Pipelined
DCD Sync SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply
• 2.5V/3.3V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
•
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• CY7C1444AV33, CY7C1445AV33 available in
JEDEC-standard lead-free 100-pin TQFP package and
lead-free and non-lead-free 165-ball FBGA package
• IEEE 1149.1 JTAG-compatible Boundary Scan
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1M x
36/2M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth- expansion Chip
Enables (CE
2
and CE
3
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3V
core power supply while all outputs operate with a +3.3V or a
+2.5V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
475
120
200 MHz
3.2
425
120
167 MHz
3.4
375
120
Unit
ns
mA
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05352 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 22, 2006
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Pin Definitions
(continued)
Name
A
0
, A
1
, A
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address locations.
Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A1:
A0 are fed to the two-bit counter..
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
X
and BWE).
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is
sampled only when a new external address is loaded.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external
address is loaded.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
2
to select/deselect the device.Not connected for BGA. Where referenced,
CE
3
is assumed active throughout this document for BGA. CE
3
is sampled only when a new
external address is loaded.
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW.
When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ “sleep” Input, active HIGH.
When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQs and DQP
X
are placed in a tri-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode Pin has an internal pull-up.
BW
A
, BW
B
BW
C
, BW
D
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
Input-
Asynchronous
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
I/O-
Synchronous
DQs, DQPs
V
DD
V
SS
V
SSQ
V
DDQ
MODE
Power Supply
Ground
I/O Ground
Input-
Static
I/O Power Supply
Power supply for the I/O circuitry.
TDO
JTAG serial output
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
Page 8 of 27
Document #: 38-05352 Rev. *E
[+] Feedback
物联网大赛方案集锦
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
