CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–V
DD
)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1422V18, CY7C1429AV18, CY7C1423V18,
CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II SIO (Double Data Rate Separate I/O)
architecture. The DDR-II SIO consists of two separate ports to
access the memory array. The Read port has dedicated Data
outputs and the Write port has dedicated Data inputs to
completely eliminate the need to “turn around’ the data bus
required with common I/O devices. Access to each port is
accomplished using a common address bus. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with two 8-bit
words in the case of CY7C1422AV18, two 9-bit words in the
case of CY7C1429AV18, two 18-bit words in the case of
CY7C1423AV18, and two 36-bit words in the case of
CY7C1424AV18, that burst sequentially into or out of the
device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to
the two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR-II SIO
SRAM in the system design. Output data clocks (C/C) enable
maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clock. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configuration
CY7C1422AV18–4M x 8
CY7C1429AV18–4M x 9
CY7C1423AV18–2M x18
CY7C1424AV18–1M x 36
Selection Guide
300 MHz
Maximum Operating Frequency
Maximum Operating Current
300
825
278 MHz
278
775
250 MHz
250
700
200 MHz
200
600
167 MHz
167
500
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 38-05617 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 26, 2006
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