• Available in 28-SOJ and 28-TSOP I Pb-Free packages
Functional Description
[1]
The CY7C1399D is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tri-state drivers. The
device has an automatic power-down feature, reducing the
power consumption when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399D is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I Pb-Free packages.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
ROW DECODER
I/O
2
SENSE AMPS
32K x 8
ARRAY
I/O
3
I/O
4
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
14
Cypress Semiconductor Corporation
Document #: 38-05467 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 10, 2005
PRELIMINARY
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
L
1399D-10
10
60
3.0
1.2
1399D-12
12
50
3.0
1.2
CY7C1399D
1399D-15
15
40
3.0
1.2
Unit
ns
mA
mA
Pin Configuration
TSOP I
Top View
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
Document #: 38-05467 Rev. *C
Page 2 of 10
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
CY7C1399D
DC Input Voltage
[2]
................................ –0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±300
mV
3.3V
±300
mV
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
Electrical Characteristics
Over the Operating Range
7C1399D-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
Output Short Circuit
Current
[3]
V
CC
Operating Supply
Current
Automatic CE Power-down
Current — TTL Inputs
Automatic CE Power-down
Current — CMOS Inputs
[4]
GND
≤
V
I
≤
V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
Max. V
CC
, CE
≥
V
IH
,
V
IN
≥
V
IH
, or V
IN
≤
V
IL
,f = f
MAX
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+1
–300
60
10
L
10
3.0
1.2
2.0
–0.3
–1
–1
Max.
7C1399D-12
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+1
–300
50
10
10
3.0
1.2
7C1399D-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power-Down
Current — TTL Inputs
Automatic CE Power-Down
Current — CMOS Inputs
[4]
GND
≤
V
I
≤
V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
Max. V
CC
, CE
≥
V
IH
,
V
IN
≥
V
IH
, or V
IN
≤
V
IL
, f = f
MAX
L
Output Short Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+1
–300
40
10
10
3.0
1.2
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
Max. V
CC
, CE
≥
V
CC
– 0.3V, V
IN
≥
V
CC
–
0.3V, or V
IN
≤
0.3V,
L
WE
≥V
CC
– 0.3V or WE
≤0.3V,
f = f
MAX
Max. V
CC
, CE
≥
V
CC
–0.3V, V
IN
≥
V
CC
–
0.3V, or V
IN
≤
0.3V, WE≥V
CC
–0.3V or
L
WE≤ 0.3V, f=f
MAX
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Device draws low standby current regardless of switching on the addresses.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05467 Rev. *C
Page 3 of 10
PRELIMINARY
Capacitance
[5]
Parameter
C
IN
: Addresses
C
IN
: Controls
C
OUT
Output Capacitance
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
5
6
6
CY7C1399D
Unit
pF
pF
pF
Thermal Resistance
[5]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[5]
Thermal Resistance
(Junction to Case)
[5]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
All – Packages
TBD
TBD
Unit
°C/W
°C/W
AC Test Loads and Waveforms
10-ns Device
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50Ω
12-ns Device
R1 317Ω
30 pF*
3.3V
OUTPUT
30pF
R2
351Ω
(a)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
INCLUDING
JIG AND
SCOPE
(b)
High-Z characteristics:
R1 317
Ω
ALL INPUT PULSES
3.0V
10%
GND
≤
3 ns
90%
90%
10%
≤
3 ns
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(c)
R2
351Ω
(d)
Switching Characteristics
Over the Operating Range
[7]
1399D-10
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[8, 9]
CE LOW to Low Z
[8]
3
0
5
3
3
10
5
0
5
3
100
10
10
3
12
5
0
6
100
12
12
3
15
6
100
15
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1399D-12
Min.
Max.
1399D-15
Min.
Max.
Unit
Notes:
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and capacitance C
L
= 30 pF.
Document #: 38-05467 Rev. *C
Page 4 of 10
PRELIMINARY
Switching Characteristics
Over the Operating Range (continued)
[7]
1399D-10
Parameter
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[10]
WE HIGH to Low
Z
[8]
3
10
8
7
0
0
7
5
0
7
3
12
8
8
0
0
8
7
0
7
3
15
10
10
0
0
10
8
0
Description
CE HIGH to High Z
[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
0
10
Min.
Max.
5
0
12
1399D-12
Min.
Max.
6
0
CY7C1399D
1399D-15
Min.
Max.
7
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
Notes:
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, t
HZWE
are specified with C
L
= 5 pF as in AC Test Loads. Transition is measured ±200 mV from steady state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
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