CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features
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Configurations
With Read Cycle Latency of 2.0 Cycles:
CY7C1246KV18 – 4 M × 8
CY7C1257KV18 – 4 M × 9
CY7C1248KV18 – 2 M × 18
CY7C1250KV18 – 1 M × 36
36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
450 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double data rate (DDR) interfaces
(data transferred at 900 MHz) at 450 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD[1]
❐
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Description
Functional Description
The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and
CY7C1250KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1246KV18), 9-bit words (CY7C1257KV18), 18-bit
words (CY7C1248KV18), or 36-bit words (CY7C1250KV18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Table 1. Selection Guide
450 MHz
450
×8
×9
× 18
× 36
590
590
600
760
400 MHz
400
540
540
550
690
375 MHz
375
520
520
530
660
333 MHz
333
480
480
490
600
Unit
MHz
mA
Maximum operating frequency
Maximum operating current
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-57834 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 24, 2011
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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Logic Block Diagram (CY7C1246KV18)
A
(20:0)
LD
K
K
DOFF
21
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
2M x 8 Array
Write
Reg
8
2M x 8 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
16
Control
Logic
CQ
CQ
8
8
DQ
[7:0]
QVLD
V
REF
R/W
NWS
[1:0]
8
8
Reg.
Reg.
Reg. 8
Logic Block Diagram (CY7C1257KV18)
A
(20:0)
LD
K
K
DOFF
21
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
2M x 9 Array
Write
Reg
9
2M x 9 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
18
Control
Logic
CQ
CQ
9
9
DQ
[8:0]
QVLD
V
REF
R/W
BWS
[0]
9
9
Reg.
Reg.
Reg. 9
Document Number: 001-57834 Rev. *B
Page 2 of 28
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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Logic Block Diagram (CY7C1248KV18)
A
(19:0)
LD
K
K
DOFF
20
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
1M x 18 Array
Write
Reg
18
1M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
36
Control
Logic
CQ
CQ
18
V
REF
R/W
BWS
[1:0]
18
18
Reg.
Reg.
Reg. 18
18
DQ
[17:0]
QVLD
Logic Block Diagram (CY7C1250KV18)
A
(18:0)
LD
K
K
DOFF
19
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
512K x 36 Array
Write
Reg
36
512K x 36 Array
CLK
Gen.
Output
Logic
Control
R/W
Read Data Reg.
72
Control
Logic
CQ
CQ
36
V
REF
R/W
BWS
[3:0]
36
36
Reg.
Reg.
Reg. 36
36
DQ
[35:0]
QVLD
Document Number: 001-57834 Rev. *B
Page 3 of 28
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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Contents
Pin Configuration ............................................................. 5
165-ball FBGA (13 × 15 × 1.4 mm) pinout .................. 5
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
DDR Operation ............................................................ 9
Depth Expansion ......................................................... 9
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
Valid Data Indicator (QVLD) ...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock ................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO) ................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in DDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Document Number: 001-57834 Rev. *B
Page 4 of 28
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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Pin Configuration
The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.
[2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1246KV18 (4 M × 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
CY7C1257KV18 (4 M × 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57834 Rev. *B
Page 5 of 28
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