CY7C1161KV18, CY7C1176KV18
CY7C1163KV18, CY7C1165KV18
18-Mbit QDR
®
II+ SRAM Four-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1161KV18 – 2 M x 8
CY7C1176KV18 – 2 M x 9
CY7C1163KV18 – 1 M x 18
CY7C1165KV18 – 512 K x 36
Separate independent read and write data ports
❐
Supports concurrent transactions
550-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
®
II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD [1]
❐
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
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Functional Description
The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and
CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to ‘turnaround’ the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1161KV18), 9-bit words (CY7C1176KV18), 18-bit
words (CY7C1163KV18), or 36-bit words (CY7C1165KV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Table 1. Selection Guide
Description
Maximum operating frequency
Maximum operating current
x8
x9
x18
x36
550 MHz
550
760
760
780
1100
500 MHz
500
710
710
720
1020
450 MHz
450
650
650
670
930
400 MHz
400
600
600
610
850
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-58911 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 24, 2011
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CY7C1161KV18, CY7C1176KV18
CY7C1163KV18, CY7C1165KV18
Contents
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 26
Ordering Code Definitions ........................................ 26
Package Diagram ............................................................ 27
Acronyms ....................................................................... 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Document Number: 001-58911 Rev. *C
Page 4 of 29
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