CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
Features
•
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
•
6 Flow-Through/Pipelined devices
— 32K x 8/9 organizations (CY7C09079V/179V)
— 64K x 8/9 organizations (CY7C09089V/189V)
— 128K x 8/9 organizations (CY7C09099V/199V)
•
3 Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
•
High-speed clock to data access 6.5
[1]
/7.5
[1]
/9/12 ns
(max.)
•
3.3V low operating power
— Active= 115 mA (typical)
—
Standby= 10
µA
(typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available
Logic Block Diagram
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
FT/Pipe
L
I/O
0L
–I/O
7/8L
[2]
0/1
1
0
0
1
0/1
FT/Pipe
R
I/O
0R
–I/O
7/8R
[2]
8/9
8/9
I/O
Control
15/16/17
I/O
Control
15/16/17
[3]
A
0
–A
14/15/16L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
–A
14/15/16R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[3]
Notes:
1. See page 6 for Load Conditions.
2. I/O
0
–I/O
7
for x8 devices, I/O
0
–I/O
8
for x9 devices.
3. A
0
–A
14
for 32K, A
0
–A
15
for 64K, and A
0
–A
16
for 128K devices.
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised May 18, 2005
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Functional Description
The CY7C09079V/89V/99V and CY7C09179V/89V/99V are
high-speed synchronous CMOS 32K, 64K, and 128K x 8/9
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory.
[4]
Registers on control, address, and data
lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid t
CD2
= 6.5 ns
[1]
(pipelined). Flow-through
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available t
CD1
= 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE
0
LOW and
CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
CNTENR
CNTENL
100-Pin TQFP
(Top View)
ADSR
CLKR
ADSL
CLKL
GND
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
A0R
A1R
A2R
A3R
A4R
A5R
A6R
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
[5]
[6]
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
[5]
A16R
[6]
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
[7]
GND
NC
A15L
A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CY7C09099V (128K x 8)
CY7C09089V (64K x 8)
CY7C09079V (32K x 8)
CNTRSTL
R/WL
OEL
[7]
FT/PIPEL
NC
NC
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/01R
GND
GND
GND
NC
VCC
VCC
NC
NC
Notes:
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. This pin is NC for CY7C09079V.
6. This pin is NC for CY7C09079V and CY7C09089V.
7. For CY7C09079V and CY7C09089V, pin #23 connected to V
CC
is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin
compatible with an IDT 5V x16 flow-through device.
Document #: 38-06043 Rev. *B
NC
Page 2 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Pin Configurations
(continued)
100-Pin TQFP
(Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
[8]
[9]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
[8]
A16R
[9]
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
A15L
A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CY7C09199V (128K x 9)
CY7C09189V (64K x 9)
CY7C09179V (32K x 9)
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/01R
GND
GND
GND
VCC
VCC
NC
Selection Guide
CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V
CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V
-6
[1]
-7
[1]
-9
-12
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns)
(Clock to Data,
Pipelined)
Typical Operating
Current I
CC
(mA)
Typical Standby Current
for I
SB1
(mA) (Both
Ports TTL Level)
Typical Standby Current
for I
SB3
(µA) (Both Ports
CMOS Level)
100
6.5
83
7.5
67
9
50
12
175
25
155
25
135
20
NC
115
20
10
µA
10
µA
10
µA
10
µA
Notes:
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V.
Document #: 38-06043 Rev. *B
Page 3 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Pin Definitions
Left Port
A
0L
–A
16L
ADS
L
Right Port
A
0R
–A
16R
ADS
R
Description
Address Inputs (A
0
–A
14
for 32K; A
0
–A
15
for 64K; and A
0
–A
16
for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted to
their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
CE
0L
,CE
1L
CLK
L
CNTEN
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
L
I/O
0L
–I/O
8L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
CNTRST
R
I/O
0R
–I/O
8R
OE
R
R/W
R
FT/PIPE
R
Maximum Ratings
[10]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with Power Applied ..–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Operating Range
Range
Commercial
Industrial
[11]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Notes:
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
Document #: 38-06043 Rev. *B
Page 4 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Electrical Characteristics
Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-6
[1]
Max.
Min.
Min.
Typ.
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
Description
Output HIGH Voltage (V
CC
= Min.
I
OH
= –4.0 mA)
Output LOW Voltage (V
CC
= Min.
I
OH
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Com’l.
Operating Current
(V
CC
= Max. I
OUT
= 0 mA)
Ind.
[11]
Outputs Disabled
Standby Current (Both
Com’l.
Ports TTL Level)
[12]
CE
L
Ind.
[11]
& CE
R
≥
V
IH
, f = f
MAX
Standby Current (One
Com’l.
[12]
CE |
Port TTL Level)
L
Ind.
[11]
CE
R
≥
V
IH
, f = f
MAX
Com’l.
Standby Current (Both
[12]
Ports CMOS Level)
Ind.
[11]
CE
L
& CE
R
≥
V
CC
– 0.2V,
f=0
Standby Current (One
Com’l.
Port CMOS Level)
[12]
Ind.
[11]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
–10
175
2.0
0.8
10
320
–10
155
275
25
95
25
85
115
175
105
165
10
250
10
10
105
135
95
125
-7
[1]
Max.
Min.
Typ.
-9
Max.
Min.
Typ.
-12
Max.
0.4
2.0
0.8
–10
135
185
20
35
95
105
10
10
85
95
10
225
295
65
75
150
160
250
250
115
125
75
100
10
250
85
140
20
50
–10
115
0.8
10
205
Unit
pF
pF
Typ.
Unit
V
V
V
V
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
2.4
0.4
2.4
0.4
2.0
0.8
10
275
390
85
120
165
210
250
250
125
170
2.4
0.4
2.0
2.4
I
SB1
I
SB2
I
SB3
I
SB4
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
10
10
Note:
12. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
AND CE
1
must be asserted to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Document #: 38-06043 Rev. *B
Page 5 of 18
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