CY7C0430BV
CY7C0430CV
10 Gb/s 3.3V QuadPort™ DSE Family
Features
• QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz
[1]
port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (max.)
• Synchronous pipelined device
— 1-Mb (64K × 18) switch array
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Width and depth expansion capabilities
• BIST (Built-In Self-Test) controller
• Dual Chip Enables on all ports for easy depth expansion
• Separate upper-byte and lower-byte controls on all
ports
• Simple array partitioning
— Internal mask register controls counter wrap-around
— Counter-Interrupt flags to indicate wrap-around
— Counter and mask registers readback on address
• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
• Commercial and industrial temperature ranges
• 3.3V low operating power
— Active = 750 mA (maximum)
— Standby = 15 mA (maximum
QuadPort DSE Family Applications
PORT 1
PORT 3
PORT 2
PORT 4
BUFFERED SWITCH
PORT 2
PORT 1
PORT 3
PORT 4
REDUNDANT DATA MIRROR
Note:
1. f
MAX2
for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation
Document #: 38-06027 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 23, 2006
CY7C0430BV
CY7C0430CV
PORT 1
PORT 2
PORT 4
PORT 3
DATA PATH AGGREGATOR
Processor 1
Pre-processed DATA Path
QuadPort
DSE Family
Processed DATA Path
Processor 2
DATA PATH MANAGER FOR
PARALLEL PACKET PROCESSING
Queue #1
PORT 1
PORT 3
Queue #2
PORT 2
PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The Quadport Datapath Switching Element (DSE) family offers
four ports that may be clocked at independent frequencies
from one another. Each port can read or write up to 133 MHz
[1]
,
giving the device up to 10 Gb/s of data throughput. The device
is 1-Mb (64K × 18) in density. Simultaneous reads are allowed
for accesses to the same address location; however, simulta-
neous reading and writing to the same address is not allowed.
Any port can write to a certain location while other ports are
reading that location simultaneously, if the timing spec for port
to port delay (t
CCS
) is met. The result of writing to the same
location by more than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
t
CD2
= 4.2 ns. Each port contains a burst counter on the input
Document #: 38-06027 Rev. *B
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV and CY7C0430CV (64K × 18 device)
supports burst contains for simple array partitioning. Counter
enable inputs are provided to stall the operation of the address
input and utilize the internal address generated by the internal
counter for fast interleaved memory applications. A port’s burst
Page 2 of 37
CY7C0430BV
CY7C0430CV
counter is loaded with an external address when the port’s
Counter Load pin (CNTLD) is asserted LOW. When the port’s
Counter Increment pin (CNTINC) is asserted, the address
counter will increment on each subsequent LOW-to- HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until
CNTINC is deasserted. The counter can address the entire
switch array and will loop back to the start. Counter Reset
(CNTRST) is used to reset the burst counter. A counter-mask
register is used to control the counter wrap. The counter and
mask register operations are described in more details in the
following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.
Top Level Logic Block Diagram
Port 1 Operation-control Logic Blocks
[2]
MRST
UB
P1
LB
P1
R/W
P1
OE
P1
CE
0P1
CE
1P1
CLK
P1
Reset
Logic
Port-1
Control
Logic
TMS
TCK
TDI
CLKBIST
JTAG
Controller
BIST
TDO
18
I/O
0P1
- I/O
17P1
CLK
P1
A
0P1
–A
15P1
MKLD
P1
CNTLD
P1
CNTINC
P1
CNTRD
P1
MKRD
P1
CNTRST
P1
INT
P1
CNTINT
P1
16
Port 1
I/O
Port 4 Logic Blocks
[3]
Port 1
Counter/
Mask Reg/
Address
Decode
Port 1
Port 4
64K × 18
QuadPort DSE
Array
Port 2
Port 3
Port 2 Logic Blocks
[3]
Port 3 Logic Blocks
[3]
Notes:
2. Port 1 Control Logic Block is detailed on page 4.
3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
Document #: 38-06027 Rev. *B
Page 3 of 37
CY7C0430BV
CY7C0430CV
Port 1 Operation-Control Logic Block Diagram
(Address Readback is independent of CEs)
R/W
P1
W
UB
P1
CE
0P1
CE
1P1
LB
P1
OE
P1
I/O
9P1
–I/O
17P1
I/O
0P1
–I/O
8P1
9
9
Port-1
I/O
Control
Addr.
Read
Port 1
Readback
Register
MRST
A
0P1
–A
15P1
CNTRD
P1
MKRD
P1
MKLD
P1
CNTINC
P1
CNTLD
P1
CNTRST
P1
CLK
P1
MRST
CNTINT
P1
Priority
Decision
Logic
16
t1
Port 1
Mask Register
Port 1
Address
Decode
Po
rt
Po
r
4
Port 1
Counter/
Address
Register
LB
P1
UB
P1
R/W
P1
CE
0P1
CE
1P1
OE
P1
CLK
P1
MRST
64K × 18
QuadPort
DSE Array
Port 1
Interrupt
Logic
INT
P1
Document #: 38-06027 Rev. *B
Page 4 of 37
Po
r
t3
Po
2
rt
CY7C0430BV
CY7C0430CV
Pin Configuration
272-ball Grid Array (BGA)
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
LB
P1
2
I/O17
P2
3
I/O15
P2
4
I/O13
P2
5
I/O11
P2
6
I/O9
P2
7
I/O16
P1
8
I/O14
P1
9
I/O12
P1
10
I/O10
P1
11
I/O10
P4
12
I/O12
P4
13
I/O14
P4
14
I/O16
P4
15
I/O9
P3
16
I/O11
P3
17
I/O13
P3
18
I/O15
P3
19
I/O17
P3
20
LB
P4
VDD1
UB
P1
I/O16
P2
I/O14
P2
I/O12
P2
I/O10
P2
I/O17
P1
I/O13
P1
I/O11
P1
TMS
TDI
I/O11
P4
I/O13
P4
I/O17
P4
I/O10
P3
I/O12
P3
I/O14
P3
I/O16
P3
UB
P4
VDD1
A14
P1
A15
P1
CE1
P1
CE0
P1
R/W
P1
I/O15
P1
VSS2
VSS2
I/O9
P1
TCK
TDO
I/O9
P4
VSS2
VSS2
I/O15
P4
R/W
P4
CE0
P4
CE1
P4
A15
P4
A14
P4
VSS1
A12
P1
A13
P1
OE
P1
VDD2
VSS2
VSS2
VDD2
VDD
VSS
VSS
VDD
VDD2
VSS2
VSS2
VDD2
OE
P4
A13
P4
A12
P4
VSS1
A10
P1
A11
P1
MKRD
P1
CNTRD
P1
CNTRD
P4
MKRD
P4
A11
P4
A10
P4
A7
P1
A8
P1
A9
P1
CNTINT
P1
CNTINT
P4
A9
P4
A8
P4
A7
P4
VSS1
A5
P1
A6
P1
CNTINC
P1
CNTINC
P4
A6
P4
A5
P4
VSS1
A3
P1
A4
P1
MKLD
P1
CNTLD
P1
GND
[4]
GND
[4]
GND
[4]
GND
[4]
CNTLD
P4
MKLD
P4
A4
P4
A3
P4
VDD1
A1
P1
A2
P1
VDD
VDD
A2
P4
A1
P4
VDD1
A0
P1
INT
P1
CNTRST
P1
CLK
P1
GND
[4]
GND
[4]
GND
[4]
GND
[4]
CLK
P4
CNTRST
P4
INT
P4
A0
P4
A0
P2
INT
P2
CNTRST
P2
VSS
GND
[4]
GND
[4]
GND
[4]
GND
[4]
VSS
CNTRST
P3
INT
P3
A0
P3
VDD1
A1
P2
A2
P2
CLK
P2
GND
[4]
GND
[4]
GND
[4]
GND
[4]
CLK
P3
A2
P3
A1
P3
VDD1
A3
P2
A4
P2
MKLD
P2
CNTLD
P2
CNTLD
P3
MKLD
P3
A4
P3
A3
P3
VSS1
A5
P2
A6
P2
CNTINC
P2
CNTINC
P3
A6
P3
A5
P3
VSS1
A7
P2
A8
P2
A9
P2
CNTINT
P2
CNTINT
P3
A9
P3
A8
P3
A7
P3
A10
P2
A11
P2
MKRD
P2
CNTRD
P2
CNTRD
P3
MKRD
P3
A11
P3
A10
P3
VSS1
A12
P2
A13
P2
OE
P2
VDD2
VSS2
VSS2
VDD2
VDD
VSS
VSS
VDD
VDD2
VSS2
VSS2
VDD2
OE
P3
A13
P3
A12
P3
VSS1
A14
P2
A15
P2
CE1
P2
CE0
P2
R/W
P2
I/O6
P2
VSS2
VSS2
I/O0
P2
NC
NC
I/O0
P3
VSS2
VSS2
I/O6
P3
R/W
P3
CE0
P3
CE1
P3
A15
P3
A14
P3
VDD1
UB
P2
I/O7
P1
I/O5
P1
I/O3
P1
I/O1
P1
I/O8
P2
I/O4
P2
I/O2
P2
MRST
CLKBIST
I/O2
P3
I/O4
P3
I/O8
P3
I/O1
P4
I/O3
P4
I/O5
P4
I/O7
P4
UB
P3
VDD1
LB
P2
I/O8
P1
I/O6
P1
I/O4
P1
I/O2
P1
I/O0
P1
1/O7
P2
I/O5
P2
I/O3
P2
I/O1
P2
I/O1
P3
I/O3
P3
I/O5
P3
I/O7
P3
I/O0
P4
I/O2
P4
I/O4
P4
I/O6
P4
I/O8
P4
LB
P3
Note:
4. Central Leads are for thermal dissipation only. They are connected to device V
SS
.
Document #: 38-06027 Rev. *B
Page 5 of 37
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