Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient Temperature (T
A
)
–40°C to +85°C
V
CC
[6]
2.2V to 3.6V
DC Electrical Characteristics
(Over the Operating Range)
CY62127DV30-45 CY62127DV30-55 CY62127DV30-70
Parameter Description
V
OH
V
OL
V
IH
Test Conditions
Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Unit
2.0
2.4
0.4
0.4
1.8
2.2
−0.3
−0.3
−1
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
0.8
+1
−0.3
−0.3
−1
2.0
2.4
0.4
0.4
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
0.8
+1
−0.3
−0.3
−1
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
µA
V
V
V
V
Output HIGH 2.2 < V
CC
< 2.7 I
OH
=
−0.1
mA
Voltage
2.7 < V
CC
< 3.6 I
OH
=
−1.0
mA
Output LOW
Voltage
Input HIGH
Voltage
2.2 < V
CC
< 2.7 I
OL
= 0.1 mA
2.7 < V
CC
< 3.6 I
OL
= 2.1 mA
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
V
IL
I
IX
I
OZ
I
CC
Input LOW
Voltage
Input
Leakage
Current
Output
Leakage
Current
V
CC
Operating
Supply
Current
Automatic CE
Power-down
Current—
CMOS Inputs
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
f = f
MAX
= 1/t
RC
V
CC
= 3.6V,
I
OUT
= 0 mA,
f = 1 MHz
CMOS level
CE > V
CC
−
0.2V,
L
V
IN
> V
CC
−
0.2V, V
IN
< 0.2V, LL
f = f
MAX
(Address and
Data Only),
f = 0 (OE, WE, BHE and
BLE)
CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or
V
IN
< 0.2V,
f = 0, V
CC
= 3.6V
L
LL
−1
+1
−1
+1
−1
+1
µA
6.5
0.85
1.5
1.5
13
1.5
5
4
5
0.85
1.5
1.5
10
1.5
5
4
5
0.85
1.5
1.5
10
1.5
5
4
mA
I
SB1
µA
I
SB2
Automatic CE
Power-down
Current—
CMOS Inputs
1.5
1.5
5
4
1.5
1.5
5
4
1.5
1.5
5
4
µA
Notes:
5. V
IL(min.)
=
−2.0V
for pulse durations less than 20 ns., V
IH(max.)
= V
CC
+0.75V
for pulse durations less than 20 ns.
6. Full device Operation Requires linear Ramp of V
CC
from 0V to V
CC
(min) & V
CC
must be stable at V
CC
(min) for 500
µs.
Document #: 38-05229 Rev. *D
Page 3 of 12
CY62127DV30
MoBL
®
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance
Parameter
θ
JA
θ
JC
Description
Thermal Resistance (Junction to Ambient)
[7]
Test Conditions
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
FBGA TSOP II Unit
55
12
76
11
°C/W
°C/W
Thermal Resistance (Junction to Case)
[7]
AC Test Loads and Waveforms
[8]
R1
V
CC
OUTPUT
C
L
= 50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R
TH
R2
ALL INPUT PULSES
V
CC
Typ
GND
10%
90%
90%
10%
Fall Time:
1 V/ns
Rise Time:
1 V/ns
THÉVENIN
EQUIVALENT
V
TH
OUTPUT
Parameters
R
1
R
2
R
TH
V
TH
2.5V (2.2– 2.7V)
16600
15400
8000
1.2
3.0V (2.7
–
3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
Parameter
V
DR
I
CCDR
t
CDR
t
R[9]
[7]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions
V
CC
=1.5V, CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
L
LL
Min.
1.5
Typ
.[4]
Max.
4
3
Unit
V
µA
ns
µs
0
200
Data Retention Waveform
[10]
V
CC
CE or
BHE. BLE
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 200
µs.
10. BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
V
CC(min.)
DATA RETENTION MODE
V
DR
> 1.5V
V CC(min.)
t
CDR
t
R
Document #: 38-05229 Rev. *D
Page 4 of 12
CY62127DV30
MoBL
®
Switching Characteristics
(Over the Operating Range)
[11]
CY62127DV30-45
[8]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[13]
t
HZBE
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[12,14]
WE HIGH to Low Z
[12]
10
45
40
40
0
0
35
40
25
0
15
10
55
40
40
0
0
40
40
25
0
20
5
70
60
60
0
0
50
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12,14]
CE LOW to Low Z
[12]
CE HIGH to High Z
[12,14]
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12]
BLE/BHE HIGH to High-Z
[12,14]
5
15
0
45
45
5
20
10
20
0
55
55
5
25
5
15
10
20
0
70
70
10
45
25
5
20
10
25
45
45
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
CY62127DV30-55
Min.
Max.
CY62127DV30-70
Min.
Max.
Unit
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
13. If both byte enables are toggled together, this value is 10 ns.
14. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
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