The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock distri-
bution applications.
The CY29350 features Xtal and LVCMOS reference clock
inputs and provides nine outputs partitioned in four banks of 1,
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4
while the other banks divide by 4 or 8 per SEL(A:D) settings,
see . These dividers allow output to input ratios of 16:1, 8:1,
4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. The internal
VCO is running at multiples of the input reference clock set by
the feedback divider, see
Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
SELA
PLL_EN
REF_SEL
PLL_EN
TCLK
VSS
XIN
XOUT
32
31
30
29
28
27
26
25
OSC
Phase
Detector
VCO
200 -
500MHz
÷2 / ÷4
QA
AVDD
FB _S E L
S E LA
S E LB
SE LC
SE LD
A V SS
XO U T
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VD D Q C
QC1
VS S
QD0
VD D Q D
QD1
VS S
LPF
÷16 / ÷32
FB_SEL
SELB
SELC
÷4 / ÷8
QB
C Y 29350
÷4 / ÷8
QC0
QC1
9
10
11
12
13
14
QD3
15
VDDQD
OE#
QD4
VSS
÷4 / ÷8
SELD
QD0
QD1
QD2
QD3
QD4
OE#
Cypress Semiconductor Corporation
Document #: 38-07474 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
VDD
QD2
XIN
16
VSS
QA
QB
REF_SEL
TCLK
VDDQB
•
408-943-2600
Revised July 26, 2004
CY29350
Pin Definitions
[1]
Pin
8
9
30
28
26
22, 24
12, 14, 16, 18, 20
2
10
31
32
3, 4, 5, 6
27
23
15, 19
1
11
7
13, 17, 21, 25, 29
XIN
TCLK
QA
QB
QC(1:0)
QD(4:0)
FB_SEL
OE#
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
AVSS
VSS
Name
XOUT
I/O
O
I
I, PD
O
O
O
O
I, PD
I, PD
I, PU
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Analog
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
VDD
Ground
Ground
Description
Oscillator Output.
Connect to a crystal.
Oscillator Input.
Connect to a crystal.
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Clock output bank D
Internal Feedback Select Input.
See
Table 1.
Output enable/disable input.
See
Table 2.
PLL enable/disable input.
See
Table 2.
Reference select input.
See
Table 2.
Frequency select input, Bank (A:D).
See
Table 2.
2.5V or 3.3V Power supply for bank B output clock
[2,3]
2.5V or 3.3V Power supply for bank C output clocks
[2,3]
2.5V or 3.3V Power supply for bank D output clocks
[2,3]
2.5V or 3.3V Power supply for PLL
[2,3]
2.5V or 3.3V Power supply for core, inputs, and bank A output
clock
[2,3]
Analog ground
Common ground
Table 1. Frequency Table
FB_SEL
0
1
Table 2. Function Table
Control
REF_SEL
PLL_EN
OE#
FB_SEL
SELA
SELB
SELC
SELD
Default
0
1
0
0
0
0
0
0
0
Xtal
Bypass mode, PLL disabled. The input
clock connects to the output dividers
Outputs enabled
Feedback divider
÷
32
÷
2 (Bank A)
÷
4 (Bank B)
÷
4 (Bank C)
÷
4 (Bank D)
÷
8 (Bank B)
÷
8 (Bank C)
÷
8 (Bank D)
1
TCLK
PLL enabled. The VCO output connects to the
output dividers
Outputs disabled (three-state)
Feedback divider
÷
16
÷
4 (Bank A )
Feedback Divider
÷32
÷16
VCO
Input Clock * 32
Input Clock * 16
Input Frequency Range
(AVDD = 3.3V)
6.25 MHz to 15.625 MHz
12.5 MHz to 31.25 MHz
Input Frequency Range
(AVDD = 2.5V)
6.25 MHz to 11.875 MHz
12.5 MHz to 23.75 MHz
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply
pins.
Document #: 38-07474 Rev. *A
Page 2 of 7
CY29350
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
[4]
Output Voltage, High
[4]
Input Current, Low
[5]
Input Current, High
[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
Functional
Relative to V
SS
Relative to V
SS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Manufacturing test
Condition
LVCMOS
LVCMOS
I
OL
= 15mA
I
OH
= –15mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
Min.
–
1.7
–
1.8
–
–
–
–
–
–
–
14
Min.
–0.3
2.375
–0.3
–0.3
200
–65
–40
150
+150
+85
+150
42
105
10
Typ.
–
–
–
–
–
–
5
–
180
210
4
18
Max.
0.7
V
DD
+0.3
0.6
–
–100
100
10
7
–
–
–
22
Max.
5.5
3.465
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
÷
2
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
2000
DC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
[4]
Output Voltage, High
[4]
Input Current, Low
[5]
Input Current, High
[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
Min.
–
2.0
–
–
2.4
––
–
–
–
–
–
–
12
Typ.
–
–
–
–
–
–
–
5
–
270
300
4
15
Max.
0.8
V
DD
+0.3
0.55
0.30
–
–100
100
10
7
–
–
–
18
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
Notes:
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07474 Rev. *A
Page 3 of 7
CY29350
AC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
[6]
Parameter
f
VCO
f
in
Description
VCO Frequency
Input Frequency
÷16
Feedback
÷32
Feedback
Bypass mode (PLL_EN = 0)
f
XTAL
f
refDC
t
r
, t
f
f
MAX
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7V to 1.7V
÷2
Output
÷4
Output
÷8
Output
DC
t
r
, t
f
t
sk(O)
t
PLZ, HZ
t
PZL, ZH
BW
t
JIT(CC)
t
JIT(PER)
t
LOCK
Output Duty Cycle
Output Rise/Fall times
Output-to-Output Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth (-3dB)
÷16
Feedback
÷32
Feedback
Cycle-to-Cycle Jitter
Period Jitter
Maximum PLL Lock Time
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.6V to 1.8V
Condition
Min.
200
12.5
6.25
0
10
25
–
100
50
25
47.5
45
0.1
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.7 - 0.9
0.6 - 0.8
–
–
–
–
–
Max.
380
23.75
11.87
200
23.75
75
1.0
190
95
47.5
52.5
55
1.0
150
10
10
–
–
150
250
100
175
1
ms
ps
ps
ns
ps
ns
ns
MHz
%
MHz
%
ns
MHz
Unit
MHz
MHz
AC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
[6]
Parameter
f
VCO
f
in
Description
VCO Frequency
Input Frequency
Condition
÷16
Feedback
÷32
Feedback
Bypass mode (PLL_EN = 0)
Min.
200
12.5
6.25
0
10
25
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
500
31.25
15.625
200
25
75
1.0
200
125
62.5
52.5
55
1.0
150
350
10
10
Unit
MHz
MHz
f
XTAL
f
refDC
t
r
, t
f
f
MAX
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷2
Output
÷4
Output
÷8
Output
MHz
%
ns
MHz
–
100
50
25
47.5
45
0.1
–
–
–
–
DC
t
r
, t
f
t
sk(O)
tsk(B)
t
PLZ, HZ
t
PZL, ZH
Output Duty Cycle
Output Rise/Fall times
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.8V to 2.4V
Banks at same voltage
Banks at different voltages
%
ns
ps
ps
ns
ns
Note:
6. AC characteristics apply for parallel output termination of 50Ω to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
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