CY2303
Phase-Aligned Clock Multiplier
Phase-Aligned Clock Multiplier
Features
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Functional Description
The CY2303 is a 3 output 3.3 V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows user to obtain 1x, 2x, and 4x REFIN output
frequencies on respective output pins.
The CY2303 has an on-chip PLL, which locks to an input clock
presented on the REFIN pin. The PLL feedback is internally
connected to the REF output. The input-to-output is
guaranteed to be less than
200
ps, and output-to-output skew
is guaranteed to be less than 200 ps.
Multiple CY2303 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
3-Multiplier configuration (1x, 2x, 4x ref)
10 MHz to 166.67 MHz operating range (reference input from
10 MHz to 41.67 MHz)
Phase alignment
80 ps typical period jitter
Output enable pin
3.3 V operation
5 V tolerant input
8-pin 150-mil small-outline integrated circuit (SOIC) package
Commercial temperature range
Logic Block Diagram
FBK
x1
REFIN
PLL
x2
REF
REFx2
x4
OE
REFx4
Cypress Semiconductor Corporation
Document #: 38-07249 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 01, 2010
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CY2303
Pinouts
Figure 1. CY2303 - 8-pin SOIC Top View
REF
GND
REFIN
N/C
1
2
3
4
8
7
6
5
OE
V
DD
REFx4
REFx2
Pin Description
Pin
1
2
3
4
5
6
7
8
REF
GND
REFIN
N/C
REFx2
REFx4
V
DD
OE
Signal
[1]
REF output (1x reference input)
Ground
Input reference frequency, 5 V tolerant input
No connect
2x reference input
4x reference input
3.3 V supply
Output enable (weak pull-up)
Description
Maximum Ratings
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC input voltage (except ref) ............... –0.5 V to V
DD
+ 0.5 V
DC input voltage REFIN ....................................–0.5 V to 7 V
Storage temperature ................................ –65 °C to +150 °C
Junction temperature................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, method 3015) ........................... > 2000 V
Operating Conditions
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply voltage
Operating temperature (ambient temperature)
Load capacitance, 10 MHz < F
OUT
< 133.33 MHz
Load capacitance, 133.33 MHz < F
OUT
< 166.67 MHz
Input capacitance
Power-up time for all V
DD
’s to reach minimum specified voltage (power
ramps must be monotonic)
Description
Min
3.0
0
–
–
–
0.05
Max
3.6
70
18
12
7
50
Unit
V
°C
pF
pF
pF
ms
Notes
1. Weak pull-down on all outputs.
Document #: 38-07249 Rev. *E
Page 2 of 9
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CY2303
Electrical Characteristics
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW voltage
Input HIGH voltage
Input LOW current
Input HIGH current
Output LOW voltage
[2]
Output HIGH voltage
[2]
Supply current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA
I
OH
= –8 mA
Unloaded outputs, REFIN = 41.67 MHz
Unloaded outputs, REFIN = 25 MHz
Unloaded outputs, REFIN = 10 MHz
Test Conditions
Min
–
2.0
–
–
–
2.4
–
–
–
Max
0.8
–
100
50
0.4
–
45
32
18
Unit
V
V
A
A
V
V
mA
mA
mA
Switching Characteristics
Parameter
1/t
1
Name
Output frequency
Duty cycle
[3]
= t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Rise time
[3]
Fall time
[3]
Output to output skew on
rising edges
[3]
18-pF load
12-pF load
Measured at V
DD
/2
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at V
DD
/2
Test Conditions
Min
10
–
40
–
–
–
–
–
–
–
Typ
–
–
50
–
–
–
–
–
80
–
Max
133.33
166.67
60
1.20
1.20
200
200
400
175
1.0
Unit
MHz
MHz
%
ns
ns
ps
ps
ps
ps
ms
Delay, REFIN rising edge to Measured at V
DD
/2 from REFIN to any output
REF rising edge
[3]
Device to device skew
[3]
Period jitter
[3]
PLL lock time
[3]
Measured at V
DD
/2 on the REF pin of the
device (pin 1)
Measured at F
OUT
< 133.33 MHz, loaded
outputs, 18-pF load
Stable power supply, valid clocks presented
on REFIN
Switching Waveforms
Figure 2. Duty Cycle Timing
t
1
t
2
V
DD
/2
Notes
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
3. All parameters are specified with loaded outputs.
Document #: 38-07249 Rev. *E
Page 3 of 9
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CY2303
Switching Waveforms
(continued)
Figure 3. All Outputs Rise/Fall Time
2.0V
0.8V
t
3
2.0V
0.8V
t
4
3.3V
0V
OUTPUT
Figure 4. Output to Output Skew
OUTPUT
V
DD
/2
OUTPUT
t
5
V
DD
/2
Figure 5. Input to Output Propagation Delay
INPUT
V
DD
/2
FBK
t
6
V
DD
/2
Figure 6. Device to Device Skew
FBK, Device 1
V
DD
/2
FBK, Device 2
t
7
V
DD
/2
Document #: 38-07249 Rev. *E
Page 4 of 9
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CY2303
Test Circuits
Figure 7. Test Circuit #1
V
DD
0.1
F
OUTPUTS
CLK
OUT
C
LOAD
GND
Document #: 38-07249 Rev. *E
Page 5 of 9
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