family. PhaseLink’s PL611s-19 offers the versatility
of using a single reference clock input and producing
up to two (kHz or MHz) system clock outputs.
Designed for low-power applications with very
stringent space requirement, PL611s-19 consumes
~1.0mA, while producing 2 distinct outputs of 27MHz
and 32kHz. The power down feature of PL611s-19,
when activated, allows the IC to consume less than
5µA of power.
The PL611s-19 fits in a small DFN, SC70, or SOT23
package. Cascading of the PL611s-19 with other
PhaseLink programmable clocks allow generating
system level clocking requirements, thereby
reducing the overall system implementation cost.
In addition, one programmable input pin can be
configured as Power Down (PDB) input, Output
Enable (OE), or Frequency switching (FSEL). The
CLK1 output can be programmed as F
REF
or CLK0.
CLK1
PIN CONFIGURATIONS
PL611s-19
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
CLK1
VDD
CLK0
OE, PDB, FSEL
FIN
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-19
1
2
3
6
5
4
CLK0
GND
GND
FIN
VDD
PL611s-19
DFN-6L
(2.0 x 1.3 x 0.6mm)
SC70-6L
(2.3 x 2.25 x 1.0mm)
SOT23-6L
(3.0 x 3.0 x 1.35mm)
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/8/08 Page 1
0.5kHz-125MHz,
MHz to KHz Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 8 bit
R = 5 bit
P = 14 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
or CLK0
Output Drive Strength
Two optional drive strengths
to choose from:
Low: 4mA
Std: 8mA (default)
Programmable
Input
TM
One output pin can be configured as:
OE - input
FSEL - input
PDB – input
PIN DESCRIPTIONS
Pin Assignment
Name
CLK1
GND
FIN
OE, PDB,
FSEL
VDD
CLK0
DFN
Pin#
2
3
1
6
5
4
SC70
Pin#
1
5
3
2
4
6
SOT
Pin #
1
2
3
4
5
6
Type
I/O
P
I
O
P
O
Description
Programmable Clock Output
GND connection
Reference input pin
This programmable input pin can be configured as an Output
Enable (OE) input, Power Down input (PDB) or On-the-Fly
Frequency Switching Selector (FSEL). This pin has an internal
pull up resistor for OE, PDB & FSEL.
VDD connection
Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
CLK1
OE
1(Default)
0
N/A
N/A
PDB
N/A
N/A
1(Default)
0
Osc.
On
On
On
Off
PLL
On
Off
On
Off
CLK0
On
Active Low
On
Active Low
When
CLK1=F
REF
On
On
On
Active Low
When
CLK1=CLK0
On
Active Low
On
Active Low
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/8/08 Page 2
0.5kHz-125MHz,
MHz to KHz Programmable Clock
FUNCTIONAL DESCRIPTION
TM
PL611s-19 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-19 accepts a reference clock input of 1MHz to 125MHz and is
capable of producing two outputs from 0.5kHz to 125MHz. This flexible design allows the PL611s-19 to deliver any
PLL generated frequency, F
REF
(Ref Clock) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design
features of the PL611s-19 are mentioned below:
PLL Programming
The PLL in the PL611s-19 is fully programmable.
The PLL is equipped with an 5-bit input frequency
divider (R-Counter), and an 8-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 14-bit post VCO divider
(P-Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
The output of CLK0 can be configured as the PLL
output (F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output,
or F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA) or Standard Drive
(8mA). The maximum output frequency is 125MHz @
3.3V, 90MHz @ 2.5V or 65MHz @ 1.8V.
Clock Output (CLK1)
The output of CLK1 can be configured as:
F
REF
– Reference (Ref Clock) Frequency
CLK0 – PLL Derived Frequency
The output drive level can be programmed to Low
Drive (4mA) or Standard Drive (8mA). The maximum
output frequency is 125MHz @ 3.3V, 90MHz @ 2.5V
or 65MHz @ 1.8V.
Programmable Input Pin (OE/PDB/FSEL)
The PL611s-19 provides one programmable I/O pin
which can be configured as one of the following
functions:
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the CLK0 output by toggling the OE pin.
Using the OE function the CLK1 clock output will
remain on when programmed as FREF and will
disable when programmed to CLK0 (See OE and PDB
Function Description on page 2). The OE pin
incorporates a 60kΩ
pull up resistor giving a default
condition of logic “1” (Enabled).
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-19 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry. In
Power Down mode the IC consumes <5µA of power.
The PDB pin incorporates a pull up resistor giving a
default condition of logic “1” (Enabled).
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-19 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60kΩ
pull up
resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/8/08 Page 3
0.5kHz-125MHz,
MHz to KHz Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
MAX.
7
V
DD
+0.5
V
DD
+0.5
260
TM
UNITS
V
V
V
C
Year
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Input (FIN) Signal Amplitude Internally AC coupled (High Frequency)
Input (FIN) Signal Amplitude
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 90%
of operating V
DD
)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% V
DD
, Std Drive, 3.3V
15pF Load, 90/10% V
DD
, Std Drive, 3.3V
PLL Enabled, @ V
DD
/2
Capacitive decoupling between V
DD
and GND.
45
2.0
2.0
50
70
0.5kHz
0.9
0.1
1
CONDITIONS
MIN.
TYP.
MAX.
125
90
65
V
DD
V
DD
125
90
65
2
10
2
3.0
3.0
55
Vpp
Vpp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
MHz
UNITS
Settling Time
Output Enable Time
Output Rise Time
Output Fall Time
Duty Cycle
Period Jitter,Pk-to-Pk*
(10K samples measured)
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/8/08 Page 4
0.5kHz-125MHz,
MHz to KHz Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic
Supply Current, Dynamic
Supply Current, Dynamic
PLL Off: Supply Current,
Dynamic
PLL Off: Supply Current,
Dynamic
PLL Off: Supply Current,
Dynamic
Supply Current, Dynamic
Operating Voltage
Power Supply Ramp
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
V
DD
t
PU
V
OL
V
OH
I
OSD
I
OSD
Time for V
DD
to reach
90% V
DD
. Power ramp
must be monotonic.
I
OL
= +4mA
I
OH
= -4mA
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
CONDITIONS
@ V
DD
=3.3V, 27MHz,
load=15pF
@ V
DD
=2.5V, 27MHz,
load=10pF
@ V
DD
=1.8V, 27MHz,
load=5pF
@ V
DD
=3.3V, 32kHz,
load=15pF
@ V
DD
=2.5V, 32kHz,
load=15pF
@ V
DD
=1.8V, 32kHz,
load=15pF
When PDB=0
1.62
MIN.
TYP.
4.0
2.7
1.1
0.6
0.5
0.2
5
3.63
100
0.4
MAX.
TM
UNITS
mA
mA
mA
mA
mA
mA
µA
V
ms
V
V
mA
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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