October 2000
®
AS6UA25616
2.3V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
‘Features
•
•
•
•
•
•
•
AS6UA25616
Intelliwatt™ active power circuitry
Industrial and commercial temperature ranges available
Organization: 262,144 words x 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
Low power consumption: ACTIVE
- 114 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41
µ
W max at 2.7V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
Row Decoder
V
CC
256K × 16
Array
(4,194,304)
V
SS
Pin arrangement (top view)
44-pin 400-mil TSOP II
44
A4
1
A5
A6
43
A3
2
A2
A7
42
3
OE
41
A1
4
A0
5
UB
40
CS
6
39
LB
I/O16
7
38
I/O1
I/O15
8
37
I/O2
I/O14
9
36
I/O3
I/O13
10
35
I/O4
V
CC
V
SS
11
34
V
SS
V
CC
12
33
13
32
I/O5
I/O12
14
31
I/O6
I/O11
15
30
I/O7
I/O10
I/O8
16
29
I/O9
17
28
WE
NC
18
A17
27
A8
19
26
A9
A16
20
25
A15
A10
24
A11
A14
21
23
A12
A13
22
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
V
SS
V
CC
I/O15
I/O16
NC
2
OE
UB
I/O11
I/O12
I/O13
I/O14
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
V
CC
V
SS
I/O7
I/O8
NC
Selection guide
V
CC
Range
Product
AS6UA25616
AS6UA25616
Min
(V)
2.7
2.3
Typ
2
(V)
3.0
2.5
Max
(V)
3.6
2.7
Speed
(ns)
55
70
Power Dissipation
Operating (I
CC
)
Max (mA)
2
1
Standby (I
SB1
)
Max (
µ
A)
20
15
10/6/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6UA25616
®
Functional description
The AS6UA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words x 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70 ns are ideal for low-power applications. Active high and low chip enables
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA25616 is guaranteed not to exceed 72
µW
power
consumption at 3.6V and 55 ns; 41µW at 2.7V and 70 ns. The device also returns data when V
CC
is reduced to 1.5V for even lower power
consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or wri e enable is
t
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to bewritten
and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.3V to 3.6V supply. Device is available in the JEDEC
standard 400-mm, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Device
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
1.0
+150
+125
20
Max
V
CC
+ 0.5
Unit
V
V
W
o
C
o
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
H
L
L
L
WE
X
X
H
H
OE
X
X
H
L
LB
X
H
X
L
H
L
L
L
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
H
X
H
L
L
H
L
L
Supply
Current
I
SB
I
CC
I
CC
I/O1–I/O8
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
I/O9–I/O16
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Mode
Standby (I
SB
)
Output disable (I
CC
)
Read (I
CC
)
I
CC
High Z
D
IN
Write (I
CC
)
2
ALLIANCE SEMICONDUCTOR
10/6/00
AS6UA25616
®
Read cycle (over the operating range)
3,9
–55
Parameter
Read cycle time
Address access time
Chip enable (CS) access
time
Output enable (OE) access
time
Output hold from address
change
CS low to output in low Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
Min
55
–
–
–
10
10
0
5
–
10
0
0
0
–
Max
–
55
55
25
–
–
20
–
55
–
20
20
–
55
Min
70
–
–
–
10
10
0
5
–
10
0
0
0
–
–70
Max
–
70
70
35
–
–
20
–
70
–
20
20
–
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
CS high to output in high Z t
CHZ
OE low to output in low Z
t
OLZ
UB/LB access time
UB/LB low to low Z
UB/LB high to high Z
t
BA
t
BLZ
t
BHZ
OE high to output in high Z t
OHZ
Power up time
t
PU
Power down time
t
PD
Key to switching waveforms
Rising input
Falling input
t
RC
Address
t
OH
D
OUT
Previous data valid
t
AA
Data valid
t
OH
Undefined/don’t care
Read waveform 1 (address
controlled)
3,6,7,9
Read waveform 2 (CS, OE, UB, LB controlled)
3,6,8,9
t
RC
Address
t
AA
OE
t
OLZ
CS
t
ACS
t
LZ
LB, UB
t
BLZ
D
OUT
t
BA
Data valid
t
BHZ
t
OHZ
t
HZ
t
OE
t
OH
4
ALLIANCE SEMICONDUCTOR
10/6/00
AS6UA25616
®
Write cycle (over the operating range)
11
–55
Parameter
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
–70
Max
–
–
–
–
–
–
–
–
20
–
–
Min
70
60
60
0
55
0
30
0
0
5
55
Max
–
–
–
–
–
–
–
–
20
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
12
12
Notes
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
Min
55
40
40
0
35
0
25
0
0
5
35
Write waveform 1 (WE controlled)
10,11
t
WC
Address
t
CW
CS
t
BW
LB, UB
t
AS
WE
t
DW
D
IN
D
OUT
Data undefined
t
WZ
Data valid
t
OW
High Z
t
DH
t
AW
t
WP
t
AH
Write waveform 2 (CS controlled)
10,11
t
WC
Address
t
AS
CS
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
D
IN
D
OUT
t
CLZ
High Z
t
WZ
Data undefined
Data valid
t
OW
High Z
t
DH
t
AH
10/6/00
ALLIANCE SEMICONDUCTOR
5
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