FX-700
Low Jitter Frequency Translator
FX-700
Description
The FX-700 is a crystal-based frequency translator used in communications applications where low jitter is paramount.
Performance advantages include superior jitter performance, high output frequencies and small package size. Advanced custom
ASIC technology results in a highly robust, reliable and predictable device. The device is packaged in a 16 pad ceramic package
with a hermetic seam welded lid.
Features
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5.0 x 7.5 mm, Hermetically sealed SMD package
Frequency Translation to 77.760 MHz
3.3 Volt or 5.0 Volt Supply
Tri-State Output allows board test
Lock Detect
Commercial or Industrial Temp. Range
CMOS Output
Absolute Pull Range Performance to +/-100 ppm
Capable of locking to an 8 kHz pulse/BITS clock
Product is free of lead and compliant to EC RoHS Directive
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Applications
Frequency Translation, Clock Smoothing
Telecom - SONET/SDH/ATM
Datacom – DSLAM, DSLAR, Access Nodes
Base Station – GSM, CDMA
Cable Modem Head End
Block Diagram
LD
(8)
C1 Charge
Pump Out
(5)
Charge
Pump
VC
OUT
(3)
VC
IN
(16)
VCXO
VCXO
OUT
(13)
FIN
(6)
÷
(1-64)
Phase
Detector
& LD
÷
(1-16384)
FOUT
(10)
V
DD
(1)
V
DB
(11)
V
DA
(2)
V
DO
(14)
VCXO
IN
(12)
TRI-STATE
(4)
GND
(7, 9)
Figure 1. Functional block diagram
Page 1 of 8
Performance Specifications
Table 1. Electrical Performance
Parameter
Frequency
4
Input Frequency
Output Frequency
Capture Range (ordering option)
Supply
Voltage
1
(V
DD
, V
DB
, V
DA
, V
DO
)
Current
5
Input
Input High Voltage
Input Low Voltage
Output
Output High Voltage
Outpuit Low Voltage
Output
Rise Time
2
Fall Time
2
Duty Cycle
3
Jitter Generation - 80.0MHz output
Operating Temp (ordering option)
Symbol
F
IN
F
OUT
APR
V
DD
V
DD
I
DD
V
IH
V
IL
V
OH
V
OL
t
R
t
F
SYM
Φ
J
T
OP
Min
0.001
0.1
Typical
Maximum
77.76
80.0
Units
MHz
MHz
ppm
±50, ±80, or ±100
4.5
2.97
5.0
3.3
5.5
3.63
40
V
V
mA
V
V
V
V
ns
ns
%
ps-rms
C
0.7*V
DD
0.3*V
DD
0.9*V
DD
0.1*V
DD
3.0
3.0
60
40
50
4.7
0/70, -40/85
1. A 0.01uF high frequency ceramic capacitor in parallel with a 0.1uF low frequency tantalum bypass capacitor is recommended
2. Figure 2 defines the waveform parameters. Figure 3 illustrates the standard test conditions under which these parameters are
tested and specified.
3. Duty Cycle is defined as (on time/period) with Vs = Vdd/2 per Figure 2. Duty Cycle is measured with a 15pf load per Figure 3.
4. Other frequencies may be available, please contact factory.
5. Combined Current From VDD, VDO, VDA, and VDB
Figure 2. Output Waveform
Figure 3. Output Test Conditions (25°C ±5°C)
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied
at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to
absolute maximum ratings for extended periods may adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Symbol
V
DD
T
STR
Ratings
7
-55 to 125
Unit
V
C
Page 2 of 8
Reliability
The FX-700 is capable of meeting the following qualification tests
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Weight
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
MSL1
Gold (1.5 um min) over Nickel (1.9 um min)
220 mg
Handling Precautions
Although ESD protection circuitry has been designed into the the FX-700, proper precautions should be taken when handling
and mounting. VI employs a human body model and a charged-device model (CDM) for ESD susceptibility testing and design
protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry
wide standard has been adopted for the CDM, a standard HBM of resistance=1.5Kohms and capacitance = 100pF is widely used
and therefore can be used for comparison purposes
Table 4. Predicted ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1500 V
1000 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
Solder Reflow Profile
Table 5. Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217 C
Time To Peak Temperature
Time At 260 C
Ramp Down
Symbol
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
3 C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6 C/sec Max
The device has been qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-
Free small body requirements. The temperatures
refer to the topside of the package, measured on
the package body surface. The FX-700 device is
hermetically sealed so an aqueous wash is not an
issue.
Figure 3. Suggested IR Profile
Page 3 of 8
Outline Drawing
Dimensions in mm.
Suggested Pad Layout
FX-700
FX-700
##M###
NNN-NNNN
NN/NN
YWWC
YWWC
Figure 5. Outline Diagram
Table 7. Pin Functions
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
V
DD
V
DA
V
COUT
Tri-state
1
C1
FIN
GND
LD
2
GNDB
FOUT
VDB
VCXO
IN
VCXO
OUT
V
DO
N.C.
V
CIN
Function
Digital PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Analog PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Control Voltage
Logic Low = Output Disable / Logic High = Output Enabled
Passive Loop Filter Node
Input Frequency
Cover and Electrical Ground
Lock Detect
Output Buffer Ground
Output Frequency
Output Buffer Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
VCXO Input
VCXO Output
VCXO Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
No Internal Connection Made
VCXO Control Voltage Input
1 Tri-state must be driven to a logic high or a logic low, there is no internal pull up or pull down resistor (tie pin to VDD for PLL operation).
2 LD is an open collector output requiring a 30k ohm minimum pull-up resistor to VDD. LD output is logic high under locked
condition, logic low for no input at FIN, and for “out-of-lock” condition LD transitions between logic low and
high at the phase detector frequency.
Page 4 of 8
Tape and Reel
Table 6. Tape and Reel Information
Tape Dimensions (mm)
A
16
B
7.5
C
1.5
D
4
E
8
F
1.5
G
20.2
Reel Dimensions (mm)
H
13
I
50
J
6
K
16.4
L
178
#/Reel
200
Figure 4. Tape and Reel
FX-700 Theory of Operation
The FX-700 includes an integrated phase detector, current mode charge pump, programmable frequency dividers and VCXO. The
FX-700 will translate an input frequency such as 8 kHz, 1.544 MHz or 19.440 MHz to a specific output frequency which is an integer
multiple (1-16384) of the input frequency and less than or equal to 77.760 MHz. For clock smoothing applications, the input
frequency is typically internally divided down by a factor of 64 (2N where N = 6) by the input frequency divider and this frequency
becomes an input to the phase detector. The integrated frequency dividers (factory programmed) and crystal based VCXO allows
for a large range of possible frequency translations and clock smoothing applications.
The FX-700’s PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input
frequency. While there will be some phase error, theory states there is no frequency error. The loop filter design will dictate many
key parameters such as jitter reduction, stability, lock range and acquisition time. The external second order passive loop filter is
a complex impedance in parallel with the input capacitance of the VCXO. The loop filter converts the charge pump output into
the VCXO’s control voltage. VI’s loop filter design methodology involves the calculation of the open loop gain bandwidth and
corresponding phase margin to determine the optimal component values that ensure high loop stability and acceptable lock in
time. As a rule of thumb, the VCXO gain is typically 100 ppm/volt and the charge pump current is typically 32 uA.
VI’s Applications Engineering staff can provide the external loop filter component values required to meet specific system
requirements and application.
Suggested FX-700 Circuit Configuration Drawing
Page 5 of 8
FPGA/CPLD
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