Common Source
Push-Pull Pair
D
G
S
S
G
S
S
D
ARF475FL
RF POWER MOSFET
N - CHANNEL PUSH - PULL PAIR
•
Specified 150 Volt, 128 MHz Characteristics:
•
Output Power = 900 Watts Peak
•
Gain = 15dB (Class AB)
•
Efficiency = 50% min
MAXIMUM RATINGS
Symbol
V
DSS
V
DGO
I
D
V
GS
P
D
T
J
,T
STG
T
L
Parameter
Drain-Source Voltage
Drain-Gate Voltage
Continuous Drain Current @ T
C
= 25°C
Gate-Source Voltage
Total Device Dissipation @ T
C
= 25°C
Operating and Storage Junction Temperature Range
Lead Temperature: 0.063" from Case for 10 Sec.
165V
450W
150MHz
The ARF475FL is a matched pair of RF power transistors in a common source configuration. It is designed for high
voltage push-pull or parallel operation in narrow band ISM and MRI power amplifiers up to 150 MHz.
•
High Performance Push-Pull RF Package.
•
High Voltage Breakdown and Large SOA
for Superior Ruggedness.
•
Low Thermal Resistance.
•
RoHS Compliant *
*Pb Free Terminal Finish.
All Ratings: T
C
= 25°C unless otherwise specified.
ARF475FL
UNIT
Volts
Amps
Volts
Watts
°C
500
500
(each device)
10
±30
910
-55 to 175
300
STATIC ELECTRICAL CHARACTERISTICS
(each device)
Symbol
BV
DSS
V
DS
(ON)
I
DSS
I
GSS
g
fs
g
fs1
g
fs2
Characteristic / Test Conditions
Drain-Source Breakdown Voltage (V
GS
= 0V, I
D
= 250
μA)
On State Drain Voltage
1
MIN
TYP
MAX
UNIT
Volts
μA
nA
mhos
500
2.9
4
100
500
±100
3
0.9
2
3.3
3.6
1.1
4
0.2
(I
D
(ON)
= 5A, V
GS
= 10V)
Zero Gate Voltage Drain Current (V
DS
= V
DSS
, V
GS
= 0V)
Zero Gate Voltage Drain Current (V
DS
= 50V, V
GS
= 0, T
C
= 125°C)
Gate-Source Leakage Current (V
GS
= ±30V, V
DS
= 0V)
Forward Transconductance (V
DS
= 15V, I
D
= 5A)
Forward Transconductance Match Ratio (V
DS
= 15V, I
D
= 5A)
Gate Threshold Voltage (V
DS
= V
GS
, I
D
= 200mA)
Gate Threshold Voltage Match (V
DS
= V
GS
, I
D
= 200mA)
/
V
GS
(TH)
DV
GS
(TH)
Volts
THERMAL CHARACTERISTICS
Symbol
R
θJC
R
θJHS
Characteristic
Junction to Case
Junction to Sink
(Use High Efficiency Thermal Grease and Planar Heat Sink Surface.)
MIN
TYP
0.15
0.30
MAX
0.165
0.33
UNIT
°C/W
050-4929 E 12-2010
CAUTION:
These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.
Microsemi Website - http://www.microsemi.com
DYNAMIC CHARACTERISTICS (per section)
Symbol
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Characteristic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
(Push-Pull Configuration)
ARF475FL
Test Conditions
V
GS
= 0V
V
DS
= 50V
f = 1MHz
V
GS
= 15V
V
DD
= 250V
I
D
= I
D[Cont.]
@ 25°C
R
G
= 1.6 W
MIN
TYP
MAX
UNIT
780
125
7
5.1
4.1
12
4.0
830
130
9
10
8
18
7
ns
pF
FUNCTIONAL CHARACTERISTICS
Symbol
G
PS
η
ψ
1
Characteristic
Common Source Amplifier Power Gain
Drain Efficiency
Electrical Ruggedness VSWR 5:1
Test Conditions
f = 128 MHz
Idq = 15mA
V
DD
= 150V
P
out
= 900W
PW = 3ms
10% duty cycle
MIN
TYP
MAX
UNIT
dB
%
14
50
16
55
No Degradation in Output Power
Pulse Test: Pulse width < 380
μS,
Duty Cycle < 2%.
Microsemi Reserves the right to change, without notice, the specifications and information contained herein.
Per transistor section unless otherwise specified.
30
I
D
, DRAIN CURRENT (AMPERES)
25
20
15
10
5
0
8V
7V
12V
11V
CAPACITANCE (pf)
10V
9V
3000
1000
500
C
oss
100
50
C
rss
C
iss
10
0
5
10
15
20
25
30
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1, Typical Output Characteristics
1
.1
1
10
100 200
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 2, Typical Capacitance vs. Drain-to-Source Voltage
30
I
D
, DRAIN CURRENT (AMPERES)
25
20
T
J
= +25°C
15
10
5
0
T
J
= -55°C
T
J
= +125°C
V
DS
> I
D
(ON) x R
DS
(ON)MAX.
250μSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
1.10
T
J
= -55°C
V
GS(th)
, THRESHOLD VOLTAGE
(NORMALIZED)
1.05
1.00
050-4929 E 12-2010
0.95
0
2
4
6
8
10
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 3, Typical Transfer Characteristics
0.90
-50 -25
0
25 50 75 100 125 150
T
C
, CASE TEMPERATURE (°C)
Figure 4, Typical Threshold Voltage vs Temperature
ARF475FL
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
10
-5
0.1
0.05
10
-4
0.5
Note:
D = 0.9
0.7
PDM
0.3
SINGLE PULSE
t1
t2
Duty Factor D =
1
/
t2
Peak TJ = PDM x Z
θJC
+ TC
t
10
-3
10
-2
10
-1
1.0
RECTANGULAR PULSE DURATION (SECONDS)
FIGURE 5a, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION
200
100
I
D
, DRAIN CURRENT (AMPERES)
OPERATION HERE
LIMITED BY R
(ON)
DS
DC Line
Dissipated Power
(Watts)
T
J
( C)
0.0755
T
C
( C)
0.0893
10
10µs
100µs
1ms
10ms
0.0135F
0.161F
Z
EXT
1
100ms
Z
EXT
are the external thermal
impedances: Case to sink, sink to
ambient, etc. Set to zero when modeling
only the case to junction.
T
C
=+25°C
T
J
=+175°C
SINGLE PULSE
0.1
1
10
100
800
Figure 5b, TRANSIENT THERMAL IMPEDANCE MODEL
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 6, Typical Maximum Safe Operating Area
Table 1 - Typical Series Equivalent Large Signal Input - Output Impedance
Freq. (MHz)
30
60
90
120
150
Zin (Ω) gate to gate
5.2 -j10
1.37 -j5.2
.53 -j2.6
.25 -j1.0
.25 +j0.2
Z
OL
(Ω) drain - drain
41 -j20
26 -j25
16 -j23
10 -j20
6.7 -j17
050-4929 E 12-2010
Zin - Gate -gate shunted with 25
Ω
I
DQ
= 15mA each side
Z
OL
- Conjugate of optimum load for 600 Watts peak output at Vdd = 150V
25% duty cycle and PW = 5ms
128MHz Test amplifier
Po = 900W @150V
3ms pulse 10% Duty Cycle
R1
J1
T1
T2
C7
C1
C8
R4
C9
Vg2
DUT
TL4
TL6
TL1
C2
TL2
C4
R2
C1 25pF poly trimmer
C2 750pF ATC 700B
C3-4 2200pF NPO 500V chip
C5-10 10nF 500V chip
C11 1000uF 250V electroytic
L1 30nH 1.5t #18 enam .375" dia
L2 680nH 12t #24 enam .312" dia
L3 2t #20 on Fair-Rite 2643006302 bead, ~ 2uH
L1
Vg1
C6
R3
L2
TL3
C3
TL5
C5
ARF475FL
+
L3
C11
C10
+
Vdd
-
T3
J2
R1-2 3.1Ω : 3 parallel 22Ω 1W 2512 SMT
R3-4 2.2kΩ 1/4W axial
T1 1:1 balun 50Ω coax on Fair-Rite 2843000102 core
T2 4:1 25Ω coax on 2843000102 Fair-Rite balun core
T3 1:1 coax balun RG-303 on 2861006802 Fair-Rite core
TL1-2 Printed line L= 0.75" w=.23"
TL3-6 Printed line L= 0.65" w=.23"
0.23" wide stripline on FR-4 board is ~ 30Ω Zo
Peak Output Power vs. Vdd and Duty Cycle
900
800
700
600
500
400
300
200
100
0
80
100
120
140
160
Drain Supply Voltage Vdd
Po Watts
Max
Duty Cycle
1.2
1
0.8
0.6
0.4
0.2
0
Notes:
The value of L1 must be adjusted as the supply voltage is
changed to maintain resonance in the output circuit. At
128MHz its value changes from approximately 40nH at
100V to 30nH at 150V.
With the 50Ω drain-to-drain load, the duty cycle above
100V must be reduced to insure power dissipation is
within the limits of the device. Maximum pulse length
should be 100mS or less. See transient thermal
impedance, figure 5.
.050
.100
.050
Thermal Considerations and Package Mounting:
± .01
.125R
4 pls
S
D1
D2
S
.325 +/1 .01
.125dia
4 pls
ARF475FL
.570
.320
The rated power dissipation is only available when the package
mounting surface is at 25°C and the junction temperature is 175°C.
The thermal resistance between junctions and case mounting sur-
face is 0.16°C/W. When installed, an additional thermal impedance
of 0.15°C/W between the package base and the mounting surface
is typical. Insure that the mounting surface is smooth and flat.
Thermal joint compound must be used to reduce the effects of
small surface irregularities. Use the minimum amount necessary to
coat the surface. The heatsink should incorporate a copper heat
spreader to obtain best results.
The package design clamps the ceramic base to the heatsink. A
clamped joint maintains the required mounting pressure while al-
lowing for thermal expansion of both the base and the heat sink.
Four 4-40 (M3) screws provide the required mounting force. T =
2.5 - 3.5
in-lb (0.28
- 0.40
N-m).
HAZARDOUS MATERIAL WARNING
1.250
S
G1
G2
S
.150
.225
.225
050-4929 E 12-2010
.150
.200
.300
.005 .040
1.500
The white ceramic portion of the device between leads
and mounting surface is beryllium oxide, BeO. Beryllium
oxide dust is toxic when inhaled. Care must be taken dur-
ing handling and mounting to avoid damage to this area.
These devices must never be thrown away with general
industrial or domestic waste.
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