Revision 14
ProASIC3L Low Power Flash FPGAs
with Flash*Freeze Technology
DS0100
Features and Benefits
Low Power
• Dramatic Reduction in Dynamic and Static Power Savings
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
• Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry to / Exit from Low-Power Flash*Freeze
Mode
• Supports Single-Voltage System Operation
• Low-Impedance Switches
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os Programmable Output
Slew Rate and Drive Strength
• Programmable Input Delay (A3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
®
3L Family
(except PQ208)
High Capacity
• 250,000 to 3,000,000 System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All
with Integrated PLL (ProASIC3EL)
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems))
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V systems
– 350 MHz: For 1.5 V systems
• ARM Cortex™-M1 Soft Processor Available with or without
Debug
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced and Pro (Professional) I/Os
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
ARM
®
Processor Support in ProASIC3L FPGAs
Table 1 • ProASIC3 Low-Power Product Family
ProASIC3L Devices
A3P250L
A3P600L
M1A3P600L
A3P1000L
M1A3P1000L
A3PE3000L
M1A3PE3000L
ARM Cortex-M1
Devices
1
System Gates
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
2
Integrated PLL in CCCs
3
VersaNet Globals
I/O Banks
Maximum User I/Os
250,000
6,144
36
8
1
Yes
1
18
4
157
600,000
13,824
108
24
1
Yes
1
18
4
235
1,000,000
24,576
144
32
1
Yes
1
18
4
300
3,000,000
75,264
504
112
1
Yes
6
18
8
620
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
June 2015
© 2015 Microsemi Corporation
I
ProASIC3L Low Power Flash FPGAs
Table 1 • ProASIC3 Low-Power Product Family
ProASIC3L Devices
A3P250L
A3P600L
M1A3P600L
VQ100
PQ208
FG144, FG256
PQ208
FG144, FG256, FG484
A3P1000L
M1A3P1000L
PQ208
FG144, FG256, FG484
A3PE3000L
M1A3PE3000L
PQ208
3
FG324, FG484, FG896
ARM Cortex-M1
Devices
1
Package Pins
VQFP
PQFP
FBGA
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
II
R evis i o n 14
ProASIC3L Low Power Flash FPGAs
I/Os Per Package
1
ProASIC3L
Low-Power
Devices
ARM
Cortex-M1
Devices
A3P250L
2
A3P600L
A3P1000L
A3PE3000L
M1A3P600L
I/O Type
M1A3P1000L
M1A3PE3000L
3
Package
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
Single-
Ended I/O
4
68
151
97
157
–
–
–
Differential
I/O Pairs
13
34
24
38
–
–
–
Single-
Ended I/O
4
Differential
I/O Pairs
–
Single-
Ended I/O
4
–
154
97
177
–
300
–
Differential
I/O Pairs
–
35
25
44
–
74
–
Single-
Ended I/O
4
–
147
Differential
I/O Pairs
–
65
154
97
177
–
235
–
35
25
43
–
60
–
–
221
341
620
–
110
168
310
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure
you are complying with design and board migration requirements.
2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.
3. ARM Cortex-M1 support is TBD on this device.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. FG256 and FG484 are footprint-compatible packages.
6. "G" indicates RoHS-compliant packages. Refer to
"ProASIC3L Ordering Information" on page IV
for the location of the "G" in the part
number.
7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user
I/Os available is reduced by one.
Table 2 • ProASIC3L FPGAs Package Sizes Dimensions
Package
Length × Width
(mm\mm)
Nominal Area
(mm
2
)
Pitch (mm)
Height (mm)
VQ100
14 × 14
196
0.5
1.00
PQ208
28 × 28
784
0.5
3.40
FG144
13 × 13
169
1.0
1.45
FG256
17 × 17
289
1.0
1.60
FG324
19 × 19
361
1.0
1.63
FG484
23 × 23
529
1.0
2.23
FG896
31 × 31
961
1.0
2.23
R ev i si o n 1 4
III
ProASIC3L Low Power Flash FPGAs
ProASIC3L Ordering Information
A3P1000L _
1
FG
G
144
I
Y
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Note: Only devices with packages greater than or equal to 5x5 are supported
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Application Temperature Range
Blank = Commercial (0°C to +85°C Junction Temperature)
I = Industrial (–40°C to +100°C Junction Temperature)
Package Lead Count
PP= Pre-Production
ES= Engineering Sample (Room Temperature Only)
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
ProASIC3L Devices
A3P250L = 250,000 System Gates
A3P600L = 600,000 System Gates
A3P1000L = 1,000,000 System Gates
A3PE3000L = 3,000,000 System Gates
ProASIC3L Devices with Cortex-M1
M1A3P600L = 600,000 System Gates
M1A3P1000L = 1,000,000 System Gates
M1A3PE3000L = 3,000,000 System Gates
Temperature Grade Offerings
Package
ARM Cortex-M1 Devices
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
A3P250L
A3P600L
M1A3P600L
A3P1000L
M1A3P1000L
–
C, I
C, I
C, I
–
C, I
–
A3PE3000L
M1A3PE3000L
C, I
C, I
C, I
C, I
–
–
–
–
C, I
C, I
C, I
–
C, I
–
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I
2
Std.
–1
?
?
?
?
IV
Revision 14
ProASIC3L Low Power Flash FPGAs
Table of Contents
ProASIC3L Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3L DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-4
3-5
3-5
3-5
Package Pin Assignments
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
R ev i si o n 1 4
V
FPGA/CPLD
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