P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
1 kB 3 V byte-erasable flash with 8-bit A/D converter
Rev. 03 — 10 July 2007
Product data sheet
1. General description
The P89LPC9102/9103/9107 are single-chip microcontrollers in low-cost 10-pin and
14-pin packages based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system-level functions have been incorporated into the P89LPC9102/9103/9107 in order
to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
I
1 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
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128-byte RAM data memory.
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Two 16-bit timer/counters (P89LPC9102/9107). Two 16-bit timers (P89LPC9103)
I
23-bit system timer that can also be used as a RTC.
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Four input multiplexed 8-bit A/D converter/single DAC output. One analog comparator
with selectable reference.
I
Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC9103/9107).
I
High-accuracy internal RC oscillator option, factory calibrated to 1 %, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable.
I
V
DD
operating range of 2.4 V to 3.6 V with 5 V tolerant I/O pins (may be pulled up or
driven to 5.5 V).
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Up to 10 (P89LPC9107) or eight (P89LPC9102/9103) I/O pins when using internal
oscillator and reset options.
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Ultra-small 10-pin HVSON package (P89LPC9102/9103). 14-pin TSSOP and DIP
packages (P89LPC9107).
2.2 Additional features
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A high performance 80C51 CPU provides instruction cycle times of 136 ns to 272 ns
for all instructions except multiply and divide when using the internal 7.3728 MHz RC
oscillator in clock doubling mode (111 ns to 222 ns when using an external 18 MHz
clock). A lower clock frequency for the same performance results in power savings and
reduced EMI.
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
I
In-Application Programming (IAP-Lite) and byte erase allows code memory to be used
for non-volatile data storage.
I
Serial flash ICP allows simple production coding with commercial EPROM
programmers. Flash security bits prevent reading of sensitive application programs.
I
Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
I
Low voltage reset (Brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
I
Idle mode and two different reduced power Power-down modes. Improved wake-up
from Power-down mode (a LOW interrupt input starts execution). Typical Power-down
mode current is
less than 1
µA
(total Power-down mode with voltage comparators
disabled).
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Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
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Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
I
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
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LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
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Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
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Only power and ground connections are required to operate the
P89LPC9102/9103/9107 when internal reset option is selected.
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Four interrupt priority levels.
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Two keypad interrupt inputs.
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Second data pointer.
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External clock input.
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Clock output (P89LPC9102/9107).
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Schmitt trigger port inputs.
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Emulation support.
3. Product comparison overview
Table 1
highlights the differences between these two devices. For a complete list of device
features, please see
Section 2 “Features”.
Table 1.
Product comparison overview
UART
-
X
X
T0 toggle/PWM
X
-
X
T1 toggle/PWM
X
-
X
CLKOUT
X
-
X
Type number
P89LPC9102
P89LPC9103
P89LPC9107
P89LPC9102_9103_9107_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
2 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
4. Ordering information
Table 2.
Ordering information
Package
Name
P89LPC9102FTK
P89LPC9103FTK
P89LPC9107FDH
P89LPC9107FN
TSSOP14
DIP14
HVSON10
Description
Version
plastic thermal enhanced very thin small outline package; no leads; SOT650-1
10 terminals; body 3
×
3
×
0.85 mm
plastic thin shrink small outline package; 14 leads; body width
4.4 mm
plastic dual in-line package; 14 leads (300 mil)
SOT402-1
SOT27-1
Type number
4.1 Ordering options
Table 3.
Ordering options
Temperature range
−40 °C
to +85
°C
Frequency
internal RC or watchdog
timer
Type number
P89LPC9102FTK
P89LPC9103FTK
P89LPC9107FDH
P89LPC9107FN
P89LPC9102_9103_9107_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
3 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
5. Block diagram
P89LPC9102
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
FLASH
internal
bus
P1.2, P1.5
PORT 1
CONFIGURABLE I/Os
128 BYTE
RAM
AD10
AD11
AD12
AD13
DAC1
ADC1/DAC1
P0[1:5], P0.7
PORT 0
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
T0
T1
CIN1A
CIN1B
KBI1
KBI2
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
TIMER 0
TIMER 1
ANALOG
COMPARATORS
PROGRAMMABLE
OSCILLATOR DIVIDER
CLKOUT
CLKIN
CPU clock
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
CONFIGURABLE
OSCILLATOR
ON-CHIP
RC OSCILLATOR
WITH CLOCK
DOUBLER OPTION
002aaa967
Fig 1. Block diagram of P89LPC9102
P89LPC9102_9103_9107_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
4 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
P89LPC9103
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
FLASH
internal
bus
P1.0, P1.1, P1.5
PORT 1
CONFIGURABLE I/Os
TXD
UART
RXD
128 BYTE
RAM
AD10
AD11
AD12
AD13
DAC1
P0[1:5]
PORT 0
CONFIGURABLE I/Os
ADC1/DAC1
KBI1
KBI2
KEYPAD
INTERRUPT
REAL-TIME CLOCK/
SYSTEM TIMER
WATCHDOG TIMER
AND OSCILLATOR
CPU
clock
TIMER 0
TIMER 1
CIN1A
CIN1B
PROGRAMMABLE
OSCILLATOR DIVIDER
ANALOG
COMPARATORS
CLKIN
CONFIGURABLE
OSCILLATOR
ON-CHIP
RC OSCILLATOR
WITH CLOCK
DOUBLER OPTION
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa968
Fig 2. Block diagram of P89LPC9103
P89LPC9102_9103_9107_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
5 of 61
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