Foil technology that adds higher reliability factor
over the traditional magnet wire used for higher
frequency circuit designs
Frequency Range up to 1MHz
Ferrite core material
Storage temperature range (component):
-40°C to +125°C
Operating temperature range: -40°C to +125°C
(ambient + self-temperature rise).
Solder reflow temperature: J-STD-020D
compliant.
•
•
•
•
•
Pb
HF
FREE
HALOGEN
Technical Data
4114
Effective October 2015
HC2LP
Low profile, high current power inductors
Product specifications
Part number
OCL
1
(μH) ±20%
l
rms2
amps (approx.)
l
sat3
amps (approx.)
DCR
4
(Ω) maximum @ 20°C
Volt-μsec
5
(V-μs)
HC2LP-R47-R
HC2LP-R68-R
HC2LP-1R0-R
HC2LP-2R2-R
HC2LP-4R7-R
HC2LP-6R0-R
.52
.63
1.15
2.00
4.55
6.00
52.9
52.9
33.0
24.3
17.0
17.0
63.75
50.00
42.50
31.90
21.25
16.50
.0006
.0006
.0013
.0023
.0046
.0046
6.87
6.87
10.31
13.75
20.62
20.62
1. Open Circuit Inductance Test Parameters: 300kHz, 0.250 Vrms, 0.0 Adc
2. DC current for an approximate temperature change of 40°C without core loss. Derating is necessary
for AC currents. PCB layout, trace thickness and width, air-flow and proximity of other heat
generating components will affect the temperature rise. It is recommended that the temperature
of the part not exceed 125°C under worst case operating conditions verified in the end application.
3. Peak current for approximately 30% rolloff.
4. Values @ 20°C
5. Applied Volt-Time product (V-μs) across the inductor. This value represents the applied V-μs at
300KHz neccessary to generate a core loss equal to 10% of the total losses for 40°C temperature rise.
Dimensions–mm
TOP VIEW
19.2
max
RECOMMENDED PCB PAD LAYOUT
10.00
FRONT VIEW
SCHEMATIC
11.18
max
1
2
9.5
typ
1
HC2LP-xxx
wwllyy R
2
19.2
max
5.50
19.00
2.8
typ
5.50
2.3
typ
xxx = Inductance value
wwllyy = Date code R = Revision level
Packaging information (mm)
Supplied in tape and reel packaging, 130 parts per 13” reel.
4.0
2.0
1.7
1.5Dia +0.10
-0.00
A
20.2
19.3
1
40.4
+/-0.1
44.0
+/-0.3
11.3
19.3
A
32
SECTION A-A
User direction of feed
2
www.eaton.com/elx
HC2LP
Low profile, high current power inductors
Core loss
Technical Data
4114
Effective October 2015
0
I
RMS
DERATING WITH CORE LOSS
% of Losses from Irms (maximum)
20
40
50
60
70
80
30
0K
Hz
20
0K
Hz
z
50
0K
H
90
92
94
95
96
97
98
99
10
20
30
% of Applied Volt- -Seconds
40
50
60
80
100
10
0K
H
200
300
1M
H
z
z
400 500 600
800 1000
Inductance Characteristics
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
OCL vs. Isat
% of OCL
80
% of I
SAT
100
120
140
160
180
200
www.eaton.com/elx
3
Technical Data
4114
Effective October 2015
HC2LP
Low profile, high current power inductors
Solder reflow profile
T
P
Max. Ramp Up Rate = 3°C/s
Max. Ramp Down Rate = 6°C/s
T
L
Preheat
A
t
t
P
T
C
-5°C
Table 1 - Standard SnPb Solder (Tc)
Package
Thickness
Volume
mm3
<350
Volume
mm3
≥350
<2.5mm)
≥2.5mm
T
smax
235°C
220°C
220°C
220°C
Temperature
Table 2 - Lead (Pb) Free Solder (Tc)
T
smin
t
s
Package
Thickness
Volume
mm
3
<350
Volume
mm
3
350 - 2000
Volume
mm
3
>2000
<1.6mm
1.6 – 2.5mm
>2.5mm
25°C
Time 25°C to Peak
260°C
260°C
250°C
260°C
250°C
245°C
260°C
245°C
245°C
Time
Reference JDEC J-STD-020D
Profile Feature
Standard SnPb Solder
Lead (Pb) Free Solder
Preheat and Soak
• Temperature min. (Tsmin)
• Temperature max. (Tsmax)
• Time (Tsmin to Tsmax) (ts)
100°C
150°C
60-120 Seconds
3°C/ Second Max.
183°C
60-150 Seconds
Table 1
20 Seconds**
6°C/ Second Max.
6 Minutes Max.
150°C
200°C
60-120 Seconds
3°C/ Second Max.
217°C
60-150 Seconds
Table 2
30 Seconds**
6°C/ Second Max.
8 Minutes Max.
Average ramp up rate Tsmax to Tp
Liquidous temperature (T
l
)
Time at liquidous (tL)
Peak package body temperature (TP)*
Time (tp)** within 5 °C of the specified classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax)
Time 25°C to Peak Temperature
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Life Support Policy: Eaton does not authorize the use of any of its products for use in life support devices or systems without the express written
approval of an officer of the Company. Life support systems are devices which support or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
Eaton reserves the right, without notice, to change design or construction of any products and to discontinue or limit distribution of any products. Eaton also
reserves the right to change or update, without notice, any technical information contained in this bulletin.
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FPGA/CPLD
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