CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
1.8V 4K/8K/16K x 16 and 8K/16K x 8
MoBL
®
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K × 16 and 8/16K x 8 organization
• High-speed access: 35 ns
• Ultra Low operating power
— Active: I
CC
= 15 mA (typical) at 55 ns
— Active: I
CC
= 25 mA (typical) at 35 ns
— Standby: I
SB3
= 2
µA
(typical)
• Small footprint: Available in a 6x6 mm 100-pin
Lead(Pb)-free fBGA
• Supports 1.8V, 2.5V, and 3.0V I/Os
• Full asynchronous operation
• Automatic power-down
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• Input Read Registers and Output Drive Registers
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Industrial temperature ranges
Selection Guide for 1.8V
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-35
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
35
25
2
2
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-55
55
15
2
2
Unit
ns
mA
µA
µA
Selection Guide for 2.5V
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-35
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
35
39
6
4
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-55
55
28
6
4
Unit
ns
mA
µA
µA
Selection Guide for 3.0V
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-35
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
35
49
7
6
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
-55
55
42
7
6
Unit
ns
mA
µA
µA
Cypress Semiconductor Corporation
Document #: 38-06081 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 31, 2005
CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
13L
I/O
0L
–I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
Right Port
CE
R
R/W
R
OE
R
A
0R
–A
13R
I/O
0R
–I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
IRR0, IRR1
ODR0-ODR4
SFEN
M/S
V
CC
GND
NC
Chip Enable
Read/Write Enable
Output Enable
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices).
Data Bus Input/Output for x16 devices; I/O
0
–I/O
7
for x8 devices.
Semaphore Enable
Upper Byte Select (I/O
8
–I/O
15
for x16 devices; Not applicable for x8 devices).
Lower Byte Select (I/O
0
–I/O
7
for x16 devices; Not applicable for x8 devices).
Interrupt Flag
Busy Flag
Input Read Register for CYDM064A16, CYDM064A08, CYDM128A16.
A13L, A13R for CYDM256A16 and CYDM128A08 devices.
Output Drive Register; These outputs are Open Drain.
Special Function Enable
Master or Slave Select
Power
Ground
No Connect. Leave this pin Unconnected.
The
CYDM256A16,
CYDM128A16,
CYDM064A16,
CYDM128A08, CYDM064A08 are available in 100-ball
0.5-mm Pitch Ball Grid Array (BGA) packages.
Power Supply
The core and I/O voltages will be 1.8V/2.5V LVCMOS/3.0V
LVTTL depending on the user's supply voltage. The supply
voltage controls both the Core and I/O voltages.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064A16, 1FFF for the CYDM128A16 and CYDM064A08,
Page 5 of 25
Description
Functional Description
The
CYDM256A16,
CYDM128A16,
CYDM064A16,
CYDM128A08, CYDM064A08 are low-power CMOS 4K,
8K,16K x 16, and 8/16K x 8 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 16-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 32-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32-bit or wider memory appli-
cations without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
Document #: 38-06081 Rev. *F
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