CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
CY7C144
CY7C145
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
• True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: I
CC
= 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pb-Free packages available
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be utilized as a standalone 64/72-Kbit
dual-port static RAM or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit
or wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications
status
buffering,
and
dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
(7C145) I/O
8L
I/O
7L
I/O
0L
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C145)
I/O
7R
I/O
0R
BUSY
R
[1, 2]
A
12R
[1, 2]
A
12L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
[2]
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R
[2]
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C144
CY7C145
Pin Configurations
(continued)
80-Pin TQFP
Top View
I/O
1L
I/O
0L
SEM
L
R/W
L
I/O
8L
A
12L
A
11L
OE
L
CE
L
NC
A
10L
V
CC
A
9L
A
8L
A
7L
64
NC
NC
A
6L
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
63
62
NC
/O
2L
/O
3L
/O
4L
/O
5L
GND
/O
6L
/O
7L
V
CC
NC
GND
/O
0R
/O
1R
/O
2R
V
CC
O
3R
O
4R
O
5R
O
6R
NC
1
2
3
4
5
6
7
8
61
NC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
CY7C145
29
30
31
32
33
34
35
36
37
38
39
NC
A
5R
R/W
R
SEM
R
I/O
7R
CE
R
GND
A
9R
A
8R
A
7R
A
12R
A
11R
A
10R
A
6R
NC
NC
NC
Pin Definitions
Left Port
A
0L−12L
CE
L
OE
L
R/W
L
SEM
L
Right Port
A
0R−12R
CE
R
OE
R
R/W
R
SEM
R
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-
icant bits of the address lines will determine which semaphore to write or read. The I/O
0
pin is used
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INT
L
is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INT
R
is set when left port writes location 1FFF and is cleared when right port reads
location 1FFF.
Busy Flag
Master or Slave Select
Power
Ground
Description
I/O
0L−7L(8L)
I/O
0R−7R(8R)
Data bus Input/Output
INT
L
INT
R
BUSY
L
M/S
V
CC
GND
BUSY
R
Selection Guide
7C144-15
7C145-15
Maximum Access Time
Maximum Operating Current
Maximum Standby Current for I
SB1
Document #: 38-06034 Rev. *C
15
220
60
7C144-25
7C145-25
25
180
40
7C144-35
7C145-35
35
160
30
7C144-55
7C145-55
55
160
30
Unit
ns
mA
mA
Page 3 of 20
I/O
8R
OE
R
NC
40
20
41
CY7C144
CY7C145
Maximum Ratings
[5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
.................−0.5V
to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
[6]
..............................................−0.5V
to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C144-15
7C145-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
GND < V
I
< V
CC
Outputs Disabled, GND < V
O
< V
CC
V
CC
= Max., I
OUT
= 0 mA
Outputs Disabled
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
CE
L
or CE
R
> V
IH
,
f = f
MAX[7]
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
125
15
130
60
−10
−10
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
0.8
+10
+10
220
−10
−10
Min.
2.4
0.4
2.2
0.8
+10
+10
180
190
40
50
110
120
15
30
100
115
mA
mA
mA
mA
Max.
7C144-25
7C145-25
Min.
2.4
0.4
Max.
Unit
V
V
V
V
µA
µA
mA
Standby Current
Both Ports
(Both Ports CMOS Levels) CE and CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
[7]
Standby Current
(One Port CMOS Level)
One Port
CE
L
or CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V, Active
Port Outputs, f = f
MAX[7]
I
SB4
Notes:
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby I
SB3
.
Document #: 38-06034 Rev. *C
Page 4 of 20
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