Si3402B-EVB
N
ON
-I
SOLATED
E
VALUATION
B
OARD
1. Description
The Si3402B non-isolated evaluation board (Si3402B-EVB Rev 2) is a reference design for a power supply in a
Power over Ethernet (PoE) Powered Device (PD) application. The Si3402B is described more completely in the
data sheet and application notes. This document describes the evaluation board. An evaluation board
demonstrating the isolated application is described in the Si3402B-ISO-EVB user’s guide.
FOR THE
Si3402B
2. Si3402B Board Interface
Ethernet data and power are applied to the board through the RJ45 connector (J1). The board itself has no
Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out
to the test points. Power may be applied in the following ways:
Connecting a dc source to pins 1, 2 and 3, 6 of the Ethernet cable (either polarity)
Connecting a dc source to pins 4, 5 and 7, 8 of the Ethernet cable (either polarity)
Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS
The Si3402B-EVB board schematics and layout are shown in Figures 1 through 6. The dc output is at connectors
J11(+) and J12(–).
Boards are generally shipped configured to produce +5 V output voltage but can be configured for +3.3 V or other
output voltages by changing resistors R5 and R6. Refer to “AN956: Using the Si3402B PoE PD Controller in
Isolated and Non-Isolated Designs” for more information. The preconfigured Class 3 signature can also be
modified according to Table 3 in AN956. The D8–D15 Schottky type diode bridge bypass is recommended only for
higher power levels (Class 3 operation). For lower power levels, such as Class 1 and Class 2, the diodes can be
removed. When the Si3402B is used in external diode bridge configuration, it requires that at least one pair of the
CTx and SPx pins be connected to the PoE voltage input terminals (to the input of the external bridge).
Rev. 1.1 4/16
Copyright © 2016 by Silicon Laboratories
Si3402B-EVB
K2
A2
K1
A1
LED_K2
LED_A2
LED_K1
LED_A1
C1
C2
C3
C4
R5 3.24K
+
1uF
12uF
1uF
1uF
TP2 NI
TP3 NI
TP4 NI
C20
NI
MX0+
CT
MX0-
8.66K
1
2
3
+
C5
22uF
560uF
R6
30 Ohm
FB1
FB
Vss
C7
1nF
C6
PWR1
7
PWR5
PWR4
PWR3
9
8
PWR2
16
17
15
18
SWO
19
20
11
10
NC
NC
FB
Vssa
SWO
VSS2
C10
C11
C12
C13
D15
D14
D13
D12
1nF
1nF
1nF
SS2150
SS2150
SS2150
SS2150
1nF
0.1uF
SP2
Vneg
RCL
HSO
RDET
L5
9
8
7
6
L3
330 Ohm
L2
C17
C16
C15
C14
330 Ohm
R3
D8
D9
D10
D11
R4
48.7
24.3k
330 Ohm
C18
10
L4
5
330 Ohm
nploss
1nF
1nF
1nF
SS2150
SS2150
SS2150
SS2150
1nF
2
R1
330
R2
49.9K
Vpos
5V
BND_POST
J11
Vpos is a EMI and ESD plane. Use top layer.
D1
PDS5100
J1
RJ-45
R9
100
J12
BND_POST
Si3402B-EVB
MX1+
CT/MX1-
MX1-
4
5
6
TP5 NI
TP6 NI
L1 33uH
At least one pair of CT1/CT2 or
SP1/SP2 should be connected.
U1
C19
NI
Connect inductor and
output filter caps
together minimizing
area of return loop
and then connect
to output ground plane.
R7
47K
C8
0.1uF
14
CT1
13
CT2
Si3402B
EROUT
NC
Vdd
NC
SP1
Vpos
1
2
3
4
12
11
Rev. 1.1
Vneg
NI = Not Installed
Optional bypass diodes for >7W applications are
in parallel with C10-C17
Vneg
Vneg is a thermal plane as wel as ESD and EMI.
Use thermal vias to at least 1 inch square plane
on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter.
Figure 1. Si3402B Schematic—5 V, Class 3 PD