Si3000SSI-EVB
E
V A L U A T I O N
B
O A R D
F
O R T H E
S
I
3000
S
TA N D A R D
S
E R I A L
I
N T E R F A C E
Description
The Si3000SSI-EVB provides the modem system
designer an easy way to evaluate the Si3000 solution.
Power is supplied through two terminal blocks, V
D
and
V
A
. This allows for 5-V or 3.3-V operation of the
evaluation board.
WITH THE
Features
The Si3000SSI-EVB includes the following:
RJ-11 Interface to Handset
RJ-11 Connections to Phone Line and Modem
Microphone, Speaker Interfaces
Line In, Line out Interfaces
Buffered Digital I/O Interface to DSP or ASIC
Recommended Layout for Key Components
Easy Power Connection for 5 V or 3.3 V Operation
Easy Power Connection for Handset
Flexible MCLK Scheme
User Selectable Serial Mode
Support for Daisy Chain Operation
Motherboard–Daughter Card Connection
Function Block Diagram
12 Volts
Motherboard
V
D
Supply
Daughter Card
Master Board
Line RJ11
Modem
DSP or
ASIC
Digital
I/O
Speaker
Out
Mic
In
Phone
Line
Si3000
Line
Out
Line
In
Handset
Select
HandSet
Master
Board
Preliminary Rev. 0.7 1/99
Line Level
Audio I/O
External I/O
Motherboard to
Daughterboard
Copyright © 1999 by Silicon Laboratories
Si3000SSI-EVB-07
Si3000SSI-EVB
Functional Description
The Si3000SSI-EVB provides an easy way to evaluate
the Si3000 solution.
This Si3000 device also supports the connection of
multiple devices on a single serial interface. The
evaluation board provides a straight forward means of
evaluating this feature.
The evaluation board consists of the Si30xxSSI-EVB
motherboard Figure 8/Figure 9 and the Si3000DC-EVB
daughter card Figure 3/Figure 4. The Si30xxSSI-EVB
can be used with other Silicon Laboratories daughter
cards, such as the Si3034DC-EVB. Contact a Silicon
Laboratories representative for more information.
In this document, the Si3000DC-EVB is occasionally
referred to “daughter card”, and the Si30xxSSI-EVB as
the “motherboard”. The Si3000SSI-EVB refers to the
system which consists of both the “motherboard” and
“daughter card.”
Clock Generation
The Si3000 requires an MCLK input. The EVB provides
two options for this requirement. MCLK can be provided
via pin 1 of JP4 (on the motherboard) from the target
system or from an oscillator installed in Y1 (on the
motherboard). JP3 (on the motherboard) selects the
MCLK source to the Si3000. In the Y1 position, the
oscillator installed in Y1 is connected. If 3.3 V is the VD
supply, Y1 must be a 3.3 V oscillator. In the JP4
position, the clock on JP4 is connected. Valid MCLK
frequency ranges from 1 to 60 MHz.
If multiple boards are cascaded together, refer to the
section on daisy-chain operation. Only the master board
will need an MCLK from Y1 or JP4.
Optional Call Progress Speaker
This feature on the Si30xxSSI-EVB is used in conjunc-
tion with the Si3034/35 evaluation boards, but is not uti-
lized by the Si3000.
Motherboard–Daughter Card Connection
JP1 and JP2 on the daughter card are used to connect
to the motherboard.
JP1 is a 3x8 socket connection to the digital signals of
the Si3000. In addition, the V
D
power of the
motherboard (J2) is routed to this socket and supplies
the power to the daughter card. JP1 connects to JP7 of
the motherboard.
JP2 is a 2x5 socket connection to the Tip and Ring and
chassis ground of the line interface to the handset
selection circuitry. JP2 connects to JP8 of the
Si30xxSSI-EVB.
Reset Circuit
The Si3000 requires an active low pulse on RESET
following power up and whenever all registers need to
be reset. Typically, the target system generates this
signal and supplies it on pin 9 of JP4 (on the
motherboard). For development purposes, the
Si3000SSI-EVB includes a reset push button, SW1, that
is a logic OR (active low) with the reset signal from the
target system. U4 (of the motherboard) provides the
reset logic and serves as a buffer. This circuit is not
necessary in a production design.
If multiple EVBs are cascaded together, the reset signal
should be generated by the master board. Using the
SW1 pushbutton on slave boards will only reset that
slave board and slave boards further down the chain.
Power Supply
Power is supplied to the Si3000SSI-EVB by means of
J2, on the motherboard, when the board is used in
stand-alone mode. If multiple boards are cascaded
together, refer to the section on daisy-chain operation
for the power supply requirements.
J2 is a euroblock header which allows for connection to
a bench power supply. J2 provides the power for all
devices connected to the V
D
node.
J2 can nominally be 3.3 V or 5 V. Note that U3 and U4
can operate from either 3.3 V or 5 V. If Y1 is used, it
must support 3.3 V operation if V
D
= 3.3 V.
J3 is used to supply power to V
A
. However, V
A
is not
used in conjunction with the Si3000DC-EVB.
Diodes D4 and D5 on the motherboard are used to
protect the Si3000SSI-EVB against over-voltage or
accidental terminal reversal. They are rated at 6.8 V.
2
Serial Modes
The Si3000 supports two different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si3000 can be
selected by JP1 and JP2 on the motherboard.
Table 1: Si3000 Serial Modes
M1
GND
GND
V
D
V
D
M0
GND
V
D
GND
V
D
Mode
FSYNC frames data
FSYNC pulse starts data frame
Slave Operation
Reserved
Preliminary Rev. 0.7
Si3000SSI-EVB
Several additional signals are required for proper
operation of the serial interface. As mentioned in the
clock generation section, an MCLK must be provided for
the Si3000 to operate.
FSYNC, SCLK, SDI and SDO are also required signals
to operate the Si3000. FSYNC provides the
sychronization for the audio samples. This signal
operates at the sample rate. A high to low transition
marks the beginning of a new frame.
SCLK is an output of the Si3000 providing the bit clock
for the audio samples. Data is valid on the falling edge
of SCLK following a FSYNC start transition. SDI is audio
samples to be transmitted and SDO is audio samples
received.
The serial port signals are also used during a secondary
frame to read and write the internal registers of the
Si3000. Refer to the Si3000 data sheet for more details
on internal registers and how to read and write those
registers.
When using the board in stand-alone mode (single), set
the motherboard switches as follows: SW2 = 1 and
SW3 = 1. Figure 1 shows a typical configuration in
stand-alone mode.
2
Table 2: Si3000SSI-EVB Modes
Configuration
Single
Slave
SW2
1
2
SW3
1
2
M1
GND
V
D
M0
X
GND
In addition to JP1 and JP2 (which control the serial
mode of the local Si3000), SW2 and SW3 are used to
route the digital signals to ensure proper connection.
The SI3000SSI-EVB can be connected as a slave
through JP6. Figure 2 shows the connection of a
Si3034SSI-EVB as a master in daisy-chain mode. See
the Si3034SSI-EVB data sheet for more details.
JP5
1
2
Speaker
Slave Board
Mic
Line
In
Line
Out
RJ11
SW2
JP4
SW3
1
Hdst Select
RJ11
RJ11
To
Modem
M1
M0
JP6
JP5
JP5
1
2
OSC
Y1
V
A
V
D
1
2
OSC
Y1
V
A
Power
SW2
To DSP
2
JP3
Power
Supply
SW2
To DSP
2
JP3
V
D
Supply
JP4
SW3
1
Master Board
M1
M0
RJ11
JP4
SW3
1
M1
JP6
M0
RJ11
JP6
Phone
Line
Figure 2. Daisy-Chain Connections
The DSP or ASIC target system connects directly to the
master board. Only the master board needs a
connection to a power supply. V
D
is routed through JP5
and JP6.
When the Si3000SSI-EVB is used as a slave board, the
serial mode must be M1 = V
D
and M0 = GND. Be sure
to configure SW2 and SW3 appropriately according to
Table 2.
Figure 1. Stand-Alone Connections
Daisy-Chain Operation
The Si3000 supports an additional serial mode which
places the device in a slave mode. This serial mode is
accomplished by M1 = V
D
and M0 = GND.
The Si3000SSI-EVB can essentially be used in two
modes: stand-alone (single) and slave. Table 2 shows
the configurations necessary for each mode.
Line Connection
The Si3000SSI-EVB has two physical interfaces
designed to connect to the phone line. One of the
connectors is on the motherboard (Figure 8), J1 pins 3
Preliminary Rev. 0.7
3
Si3000SSI-EVB
and 4, while the other connector is on the daughter card
(Figure 3). These interfaces are equivalent and
interchangeable. When using the Si3000SSI-EVB in
stand-alone mode, only one of these line interfaces is
used.
When using the Si3000SSI-EVB in slave mode, one of
the line interfaces is used to connect to the phone line,
while the other line interface is used to connect to the
Master Board Modem Line Interface. This way, both the
Si3000SSI-EVB and Si3034SSI-EVB gain access to the
phone line without requiring an external phone splitter.
Microphone Interface
A standard 3.5 mm mini-phono connector located on the
daughter card connector J2 is used to provide an
interface from an external microphone to the Si3000.
The input impedance to MIC input of the Si3000 is at
least 10 k
Ω
. The Si3000 has a programmable pre-
amplification to support many input line levels.
If Jumper JP3 on the daughter card is populated, the
microphone can be powered directly from the Si3000
MBIAS output. The MBIAS output provides a typical
voltage of 2.5 volts and can supply up to 5 mA,
programmable through an external resistor. For
applications that cannot be met by the Si3000’s MBIAS
output, the jumper may be removed and an external
biasing voltage can be applied to the microphone.
Handset Interface
The Si3000SSI-EVB includes a handset interface. This
interface is located on the daughter card J1 connector
pins 9 and 10.
A handset can connect directly to the phone line or the
the Si3000 device. The target system is expected to
control the DPDT relay to select the handset
connection. When the handset is connected to the
Si3000, both the Si3000 and handset are disconnected
from the phone line. In this case, the Si3000SSI-EVB
supplies DC power to the handset through an external
12 VDC bench supply. The euroblock header, J6, on the
daughter card is provided for this connection. 24.5 mA
of DC loop current is supplied to the handset.
In a voice modem application, the Si3000SSI-EVB is
configured in the slave mode, with an Si3034SSI-EVB
acting as the master board. When this system is in the
on-hook state, either the Si3034 or the handset can
respond to the phone ring and place the system in the
off-hook state.
If the system software chooses to allow the Si3034 EVB
to go off hook, the handset is excluded from the phone
loop and is connected directly to the Si3000 EVB. Voice
traffic is handled by the Si3000 and system software is
responsible for creating a virtual voice connection
between the handset and the phone system through the
Si3000 and Si3034 devices.
Speaker Interface
A standard 3.5 mm mini-phone connector is located on
the daughter card connector J3. The Si3000 SPKRR
and SPKRL outputs are designed to drive 60
Ω
loads
directly. To drive a 32
Ω
headset, an external series
resistor (30
Ω)
is needed. Driving a 32
Ω
headset
directly may result in reduced THD and Dynamic Range
performance. The maximum voltage swing is 1 Vrms for
either the left or right speaker drivers. The Si3000
speaker
outputs
have
programmable
analog
attenuation.
Line Input Interface
A standard RCA jack on the daughter card connector J5
is used to provide the line-level audio inputs to the
Si3000. The Si3000 has a programmable pre-amplifier.
The input impedance of the LINEI is at least 10 k
Ω
. The
Si3000 supports multiple levels of pre-amplification to
support various line-levels.
Line Output Interface
A standard RCA jack on the daughter card connector J4
is used to provide the line-level audio outputs from the
Si3000. The Si3000 line output gain is programmable.
The maximum output voltage is 1 Vrms.
4
Preliminary Rev. 0.7
Preliminary Rev. 0.7
Si3000SSI-EVB
Figure 3. Si3000DC-EVB Schematic Page 1
5
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