Si4702/03-C19
B
RO A D C A S T
F M R
A DI O
T
U N E R FO R
P
O RTA BL E
A
PP L I C A T I O N S
Features
This data sheet applies to
Si4702/03-C Firmware 19 and
greater
Worldwide FM band support
(76–108 MHz)
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
Seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis
(50/75 µs)
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control
interface
2.7 to 5.5 V supply voltage
Integrated LDO regulator
allows direct connection to
battery
3 x 3 mm 20-pin QFN package
Ordering Information:
See page 38.
Pb-free/RoHS compliant
RDS/RBDS Processor (Si4703)
Integrated crystal oscillator
Pin Assignments
(Top View)
Si4702/03-GM
GPIO1
GPIO2
GPIO3
17
10
V
IO
NC
Applications
Cellular handsets
MP3 players
Portable radios
USB FM radio
PDAs
Notebook PCs
Portable navigation
Consumer electronics
NC
FMIP
RFGND
GND
RST
1
2
3
4
5
6
SEN
20
19
18
Description
The Si4702/03 integrates the complete tuner function from antenna input
to stereo audio output for FM broadcast radio reception.
GND
PAD
7
SCLK
8
SDIO
9
RCLK
Functional Block Diagram
Headphone
Cable
FMIP
RFGND
LNA
PGA
Q
ADC
I
ADC
Si4702/03
DAC
U.S. and International Patents
AMPLIFIER
LOUT
DSP
FILTER
DEMOD
MPX
AUDIO
pending—Abbreviated U.S. Patent
List:
7272375, 7127217, 7272373,
7272374, 7321324, 7339503,
7339504, 7355476, 7426376,
DAC
ROUT
AGC
32.768 kHz
0 / 90
LOW-IF
GPIO
GPIO
CONTROLLER
VIO
CONTROL
INTERFACE
RCLK
TUNE
AFC
RDS
(Si4703)
RST
SDIO
SCLK
SEN
7436252, 7471940
2.7–5.5 V
VA
VD
REG
XTAL
OSC
RSSI
Rev. 1.1 7/09
Copyright © 2009 by Silicon Laboratories
Si4702/03-C19
V
A
16
15 GND
14 LOUT
13 ROUT
12 GND
11 V
D
Si4702/03-C19
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1. Si4702 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Package Outline: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. PCB Land Pattern: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.1
3
Si4702/03-C19
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Digital Power Supply Power-Up
Rise Time
Analog Power Supply Power-Up
Rise Time
Interface Power Supply Power-Up
Rise Time
Ambient Temperature
Symbol
V
D
V
A
V
IO
V
DRISE
V
ARISE
V
IORISE
T
A
Test Condition
Min
2.7
2.7
1.5
10
10
10
–20
Typ
—
—
—
—
—
—
25
Max
5.5
5.5
3.6
—
—
—
85
Unit
V
V
V
µs
µs
µs
°C
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
D
= V
A
= 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings
1,2
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Input Current
3
Input Voltage
3
Operating Temperature
Storage Temperature
RF Input Level
4
Symbol
V
D
V
A
V
IO
I
IN
V
IN
T
OP
T
STG
Value
–0.5 to 5.8
–0.5 to 5.8
–0.5 to 3.9
±10
–0.3 to (V
IO
+ 0.3)
–40 to 95
–55 to 150
0.4
Unit
V
V
V
mA
V
°C
°C
V
pK
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2.
The Si4702/03-C19 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling
and assembly of this device should only be done at ESD-protected workstations.
3.
For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
4.
At RF input pins.
4
Rev. 1.1
Si4702/03-C19
Table 3. DC Characteristics
1
(V
D
= V
A
= 2.7 to 3.6 V, V
IO
= 1.5 to 3.6 V, T
A
= –20 to 85 °C)
Parameter
Analog Operating Supply Current
2
Digital Operating Supply Current
2
Interface Operating Supply
Current
2
Total Operating Supply
Current
2,3,4,5
Total Operating Supply
Current
2,3,4
Total Operating Supply
Current
2,3,4,6
Total Operating Supply
Current
2,3,4,6
Analog Powerdown Supply Current
2,7
Digital Powerdown Supply Current
2,7
Interface Powerdown Supply
Current
2,7
Total Powerdown Supply Current
2,7
High Level Input Voltage
8
Low Level Input Voltage
8
High Level Input Current
8
Low Level Input Current
8
High Level Output Voltage
9
Low Level Output Voltage
9
Symbol
I
A
I
D
I
IO
I
OP
I
OP
I
OP
I
OP
Test Condition
ENABLE = 1
ENABLE = 1
ENABLE = 1
ENABLE = 1
Low SNR signal
ENABLE = 1
ENABLE = 1
RDS = 1
ENABLE = 1
RDS = 1,
Low SNR signal
ENABLE = 0
ENABLE = 0
ENABLE = 0
SCLK, RCLK inactive
ENABLE = 0
Min
—
—
—
—
—
—
—
Typ
10.8
3.3
0.3
15.3
14.4
14.9
15.8
Max
—
—
—
16.8
15.9
16.4
16.8
Unit
mA
mA
mA
mA
mA
mA
mA
I
APD
I
DPD
I
IOPD
I
PD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
—
—
—
—
0.7 x V
IO
–0.3
3.5
2.5
2.5
8.5
—
—
—
—
—
—
—
—
—
12.0
V
IO
+ 0.3
0.3 x V
IO
10
10
—
0.2 x V
IO
µA
µA
µA
µA
V
V
µA
µA
V
V
V
IN
= V
IO
= 3.6 V
V
IN
= 0 V,
V
IO
= 3.6 V
I
OUT
= 500 µA
I
OUT
= –500 µA
–10
–10
0.8 x V
IO
—
Notes:
1.
All specifications for the Si4702 unless otherwise noted.
2.
Refer to Register 02h, "Power Configuration" on page 24 for ENABLE bit description.
3.
The LNA is automatically switched to higher current mode for optimum sensitivity in low SNR conditions.
4.
Analog and digital supply currents are simultaneously adjusted based on SNR level.
5.
Stereo and RDS functionality are disabled at low SNR levels.
6.
RDS functionality only available for Si4703.
7.
Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 19.
8.
For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
9.
For output pins SDIO, GPIO1, GPIO2, and GPIO3.
Rev. 1.1
5
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