S i 3 0 x x P P T- E V B
E
VALUATION
B
OARD
Description
The Si30xxPPT-EVB provides the telecommunications
system engineer an easy way to evaluate the
functionality of Silicon Laboratories’ Si30xx (Si3034,
Si3035, Si3044, Si3056/18, and Si3056/19) integrated
voice direct access arrangement (DAA) solution. The
digital side of the chipset (Si3021 or Si3056) has a DSP
serial interface as well as system-side DAA
functionality. In conjunction with the Si3012/14/15 or
Si3018/19 global line-side silicon DAA chip, it provides
a low-cost, solid-state, globally-compliant voice DAA
solution. The Si30xx chipset can be easily controlled
from a PC using the supplied application software
(requires software Rev 2.0 or above and FPGA Rev 2.0
or above).
FOR THE
Si30
XX
Features
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Ability to read and write DAA registers
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain
Recommended layout for key components
Daisy-chain support
Functional Block Diagram
Motherboard
Daughter Card
SSI
DSP side
DAA
Line Side
DAA
FPGA
PPT
BOM
TIP
RING
Preliminary Rev. 1.0 1/03
Copyright © 2003 by Silicon Laboratories
Si30xxPPT-EVB-10
Si30xxPPT-EVB
Functional Description
The Si30xxPPT-EVB provides the telecommunications
system engineer an easy way to evaluate the Si30xx
solution. Silicon Labs’ DAAs are integrated direct
access arrangements that provide a digital, low-cost,
solid-state interface to worldwide telephone lines.
Through the patented ISOcap technology, the Si30xx
eliminates the need for an analog frond end (AFE), an
isolation transformer, relays, opto-isolators, and a 2 to
4-wire hybrid.
The Si30xxPPT-EVB also supports the connection of
multiple devices on an SSI interface. The evaluation
board provides a straightforward means of evaluating
this feature.
The evaluation board consists of the Si30xxPPT-EVB
Si-LINK (mother) board and the Si30xxDC_EVB
daughter card. A custom ribbon cable is also provided
to connect to the parallel port of a PC. Contact a Silicon
Laboratories representative for more information.
clock to the DAA. The FPGA is designed to use a
18.432 MHz oscillator (included with the board).
Optional Call Progress Speaker
The AOUT pin of the digital-side device provides a call
monitoring feature. U3 provides 25 dB of signal gain on
this output. The AOUT pin has an output impedance of
10 kW. R9 and R10 form a voltage divider that provides
a gain of –24.4 dB. This divider is necessary so the
LM386, which is operating from a +5 V supply, is not
overdriven. The LM386 is a cost-effective low-power
amplifier capable of driving many different buzzers or
speakers. In the case of cascaded evaluation boards,
the AOUT signal is local to each board.
Reset Circuit
The Si30xx requires an active low pulse on RESET
following powerup and whenever all registers need to
be reset. For development purposes, the Si30xxPPT-
EVB includes a reset push button, SW1, that is used by
the FPGA to generate a reset pulse of the DAA.
If multiple boards are cascaded together, the reset
signal should be generated by the master board. Using
the SW1 pushbutton on slave boards does not reset
that slave board.
Motherboard-Daughter Card Connection
The Si30xxDC-EVB connects to the Si30xxPPT-EVB
through two sockets: JP1 and JP2. JP1 is a 3x8 socket
connection to the digital signals of the DSP-side chip, as
well as to the analog AOUT pin. In addition, a 3.3 V
regulated supply is routed to this socket and supplies
the power to the digital-side device. JP1 of the daughter
card connects to JP2 of the Si30xxPPT-EVB. JP2 is a
2x5 socket connection from the TIP and RING and
chassis ground of the line interface to the line-side
device. JP2 of the Si30xx DC-EVB connects to JP1 of
the Si30xx PPT EVB.
Serial Modes
The Si30xx supports several different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si30xx can be
selected by JP3 and JP4.
Line Connection
J1 is provided to connect the EVB to a standard RJ-11
connector. The system cannot execute an off-hook
command without the phone line connected. This
condition can be detected by examining the FDT bit of
register 12 or by simply observing that there is no dial
tone on the DSP or ASIC.
Power Supply
Power is supplied to the EVB by means of J3 or J4. J3
is a euroblock header that allows for connection to a
bench power supply. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the onboard voltage
regulator also works with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the Si30xxPPT-EVB. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the FPGA. A third regulator
provides 2.5 V for the core voltage of the FPGA.
PC Parallel Port
JP13 connects through the Silicon Labs custom ribbon
cable to the parallel port of the PC. The parallel port
connection allows the designer to read and write the
DAA register using the evaluation software included
with the Si30xxPPT-EVB.
Clock Generation
The Si30xx requires an MCLK input. An on-board
oscillator (Y1) is used by the FPGA to clock all the
subsystems as well as generate and provide the master
2
Preliminary Rev. 1.0
Si30xxPPT-EVB
Configuring the Si30xxPPT-EVB
The S30xxPPT-EVB is used to interface the Si30xx
chipset to a PC or other audio system for easy
evaluation. It uses an FPGA to translate the parallel port
interface to the SSI bus to communicate to the Si30xx.
The audio data and control data are communicated from
the controlling PC using the aforementioned software.
This mode allows the user to evaluate the DAA without
any lab equipment other than a PC.
When in mode 0, the negative edge of FSYNC indicates
the starting of the frame, and FSYNC is low until the end
of data transfer. By selecting mode 1 operation, the
rising edge of FSYNC indicates the start of the frame,
but is only high for one cycle. To evaluate the Si30xx’s
multiple device operation, chain the slave boards with
JP3 and JP4 set to mode 2. See Table 1 for a
description of these operating modes.
The Si30xxPPT-EVB has the ability to interface in two
different modes of the SSI bus: 5-bit address space
operation is used for the Si3034/35/44, and 7-bit
address space operation is used for the Si3056. Table 2
shows how to configure the Si30xxPPT-EVB to operate
in a desired SSI operational mode.
Table 2. SSI Operational Mode Configuration
Mode
5-bit Addr
7-bit Addr
Sel0
0
1
Description
For Si3021 digital side
For Si3056 digital side
Table 1. Mode Configuration
Mode M1 M2
0
1
2
3
0
0
1
1
0
1
0
1
Description
FSYNC frames data
FSYNC pulse starts data frame
Slave mode
Reserved
Preliminary Rev. 1.0
3
Si30xxPPT-EVB
Evaluation Software
The Si30xxPPT-EVB includes an easy-to-use graphical
interface for controlling the evaluation platform. This
software allows the system designer to characterize the
Si30xx DAA performance without constructing any
custom hardware. The evaluation software includes the
following features:
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Run:
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Exit: Stops the program
Save: Stores the audio waveform into .wav files
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Configure:
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Configure DAA: Display hardware status and user
configuration. User can set advanced software options.
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Reset DAA: Resets DAA and executes basic
initialization sequences on Reg 1, Reg 6–10, and Reg 14.
Ability to read and write DAA registers using the SSI
bus
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain using the SSI bus
Daisy-chain support
Transmit and receive path attenuation and gain
settings
Ring detection
Loop current measurement
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Design Tool
Register Map: Displays Register Map of Si30xx
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Signal Flow Diagram: Displays Signal Flow Diagram of
Si30xx.
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Transhybrid Loss Calculation: Calculate transhybrid loss
over frequency
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Ringing: Helps user program ring validation registers.
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Help:
Displays information about the evaluation
board
PC System Requirements
The application software for the Si30xxPPT-EVB has
the following system requirements:
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Windows98 or Windows2000
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Available parallel port
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EPP or ECP parallel port mode for Windows 98
EPP parallel port mode for Windows 2000
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450 MHz Pentium II or greater recommended
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64 MB of memory or greater recommended
Installation
The supplied CD contains the Si30xxPPT-EVB windows
driver files as well as a setup utility for installing the
evaluation software.
To install the Si30xxPPT-EVB software, run the
installation program on the “Silicon Laboratories
Wireline Software CD.” The path for the installation
program is Si30xx Evaluation Software\setup.exe. The
installer guides the user through the installation process
for Si30xxPPT-EVB.exe and the LabVIEW Run-Time
engine.
Using the Si30xxPPT-EVB
Application Software
A shortcut for starting the application software that
controls the Si30xxPPT-EVB is installed in the Windows
Start Menu under the Programs folder in the “Si30xx
Evaluation Software” folder.
Application Menus
Three pulldown menus are used to configure the
operation of the software:
4
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 1. Si30xxPPT-EVB Evaluation Software in the Audio Data Monitoring View
Audio Data Monitoring View
The audio data monitoring view is discussed in the
following sections.
Receive Audio Data of Channel#
Allows selection of channel to control and view. The
Audio Data Monitoring view allows the generation of
DAC data and the capture and display of ADC data.
Operation of the front panel in Line Monitoring view is
detailed in the following list. See Figure 1.
TX Control
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DAC Waveform:
Selects the waveform to be
generated by the DAC. The waveform types are as
follows: dc, Sine, Square, Ramp, and .wav file.
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TX Gain (dB):
Selects the transmit path gain/
attenuation.
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TX Mute:
Mutes the transmit path.
Sampling Rate:
Sets the sampling rate of the DAA
and performs writes to corresponding registers.
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Amplitude:
Sets the amplitude of the DAC
waveform in either volts or the units of DAC codes.
The units are determined by the Amplitude Units
control.
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Frequency:
Selects the frequency (Hz) of the
waveform to generate. The actual waveform
frequency may vary slightly from the entered value.
This variation is due to the requirement to fit an
integer number of samples into the transmit buffer.
The control is updated to reflect the actual waveform
frequency generated. The equation for calculating
the frequency of the waveform is as follows:
Actual Frequency = round ((Waveform Frequency/DAC
Sample Rate) x BufferSize) x (DAC Sample Rate/
BufferSize)
Preliminary Rev. 1.0
5
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