Si3050-EVB
S i 3 0 5 0 E
V A L U A TI O N
B
O A R D S
: S i 3 0 5 0 P P T- E V B , S i 3 0 5 0 P P T 1 - E V B ,
S i 3 0 5 0 F M P P T- E V B
Description
The
Si3050
evaluation
boards
provide
the
telecommunications system engineer an easy way to
evaluate the functionality of Silicon Laboratories’
Si3050/Si3019 or Si3050/3018 integrated voice direct
access arrangement (DAA) solutions. The Si3050
integrates an SPI, PCM, and GCI serial interface as well
as system-side DAA functionality. In conjunction with
the Si3019 or Si3018 global line-side silicon DAA chip, it
provides a low-cost, solid-state, globally-compliant
voice DAA solution.
There are three different Si3050 evaluation boards
available:
The Si3050PPT-EVB allows evaluation of the
Si3050 and Si3019 devices in TSSOP packages.
The Si3050PPT1-EVB allows evaluation of the
Si3050 and Si3018 devices in TSSOP packages.
The Si3050FMPPT-EVB allows evaluation of the
Si3050 and Si3019 devices in QFN packages.
The Si3050 evaluation boards can be easily controlled
from a PC using the supplied application software.
Features
Ability to read and write DAA registers
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain
Recommended layout for key components
Daisy-chain support
Functional Block Diagram
Si-LINK
FPGA
PPT
SPI
Daughter Card
Si3050
Si3019
BOM
TIP
RING
BNC/Audio
Precision Box
PCM/GCI
Optional
Speaker
Optional
Ground Start
Circuit
Rev. 1.1 7/11
Copyright © 2011 by Silicon Laboratories
Si3050-EVB
Si3050-EVB
1. Functional Description
The
Si3050
evaluation
boards
provide
the
telecommunications system engineer an easy way to
evaluate the Si3050 plus Si3018/3019 solution. Silicon
Labs’ DAAs are integrated direct access arrangements
that provide a digital, low-cost, solid-sate interface to
worldwide telephone lines. Through the patented
ISOcap™ technology, these chipsets eliminate the need
for an analog frond end (AFE), an isolation transformer,
relays, opto-isolators, and a 2- to 4-wire hybrid.
The Si3050 evaluation boards also support the
connection of multiple devices on an SPI/PCM
interface. The evaluation boards provide a
straightforward means of evaluating this feature.
The evaluation board consists of the Si-LINK
motherboard and one of the three available Si3050
daughter cards. A custom ribbon cable is also provided
to connect to the parallel port of a PC. Contact a Silicon
Laboratories representative for more information.
1.2. Power Supply
Power is supplied to the Si-LINK motherboard by
means of J1 and J4. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the on-board voltage
regulator will also work with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the motherboard. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the motherboard's FPGA. A third
regulator provides 2.5 V for the core voltage of the
FPGA. J1 is a no-connect in this application.
1.3. Clock Generation
The Si3050 requires an FSYNC, PCLK, and SCLK
input. An on-board oscillator (Y1) is used by the FPGA
to clock all the subsystems as well as generate and
provide the FSYNC, PCLK, and SCLK to the DAA.
FPGA is designed to use a 32.768 MHz oscillator
(included with the board).
1.1. Motherboard-Daughter Card Connec-
tion
The Si3050 daughter card connects to the Si-LINK
motherboard through five sockets, JS1–JS5. JS1 is a
5x2 socket and JS2 is a 2x2 socket connecting SPI
digital signals of the Si3050. JS3 is a 5x2 socket
connection reserved for future use. JS4 is a 5x2 socket
connection that routes the Vdd regulated supply. JS5 is
a 5x2 socket connection to the PCM digital signals of
the Si3050. JS3 is a no-connect in this application.
1.4. Reset Circuit
The Si3050 chipset requires an active low pulse on
RESET following power up and whenever all registers
need to be reset. For development purposes, the Si-
Link motherboard includes a reset push button, SW1,
that is used by the FPGA to generate a reset pulse of
the DAA.
1.5. Line Connection
J1 is provided to connect the Si3050 daughter board to
a standard RJ-11 connector. The system cannot
execute an off-hook command without the phone line
connected.
1.6. PC Parallel Port
JP2 and P3 connect through the Silicon Labs custom
ribbon cable to the parallel port of the PC. The parallel
port connection allows the designer to read and write
the DAA registers using the evaluation software
included with the evaluation board.
2
Rev. 1.1
Si3050-EVB
2. Configuring the Si-LINK
The Si-LINK motherboard is used to interface the
Si3050 to a PC or other audio system for easy
evaluation. It uses an FPGA to translate the parallel port
interface to either SPI/PCM, SPI-only, or GCI to
communicate with the Si3050.
When in SPI/PCM mode, the PCM audio data and SPI
control data are communicated from the controlling PC
using the aforementioned software. This mode allows
the user to evaluate the DAA without any lab equipment
other than a PC.
By selecting SPI-only operation, the PC is still used to
control the DAA through the SPI bus, but the PCM
audio data is routed from an external source. This
external source may be an Audio Precision system
using the P1 and P2 headers or a PCM highway using
the BNC connectors, J5–J8 (not populated).
To evaluate the Si3050’s operation with the GCI
interface, the PC may be used to send the audio data
and control. The FPGA performs the necessary
translation to communicate to the Si3050 in this mode.
The fourth mode of operation is the pass-thru mode. In
this mode, the FPGA is only used to route the GCI bus
to the Audio Precision or BNC headers on the Si-LINK
board. In this mode, a PC is not required to control the
evaluation platform.
Mode
SPI/PCM
SPI-Only
GCI
Pass-Thru
JP3 (Source)
0
1
0
1
JP4 (Format)
0
0
1
1
By changing the jumper configuration prior to powering
the board, the mode of the board can be set according
to Tables 1–3.
JP10 is the sixth jumper on the Si-LINK motherboard.
Moving this jumper to the INT position routes pin 9 of
the Si3050 to the Si-LINK motherboard. When the
jumper is in the AOUT position, this signal is routed to
the optional call progress speaker system, which is not
populated by default on the evaluation platform. Refer to
the AOUT PWM circuit in the Si3050 data sheet for
values used to populate this circuit.
Table 1. PCM or GCI Highway Mode Selection
SCLK
1
0
0
SDI
X
0
1
Mode Selected
PCM Mode
GCI Mode,
B2 Channel used
GCI Mode,
B1 Channel used
Note:
Values shown are the states of the pins at the
rising edge of RESET.
Table 2. Pin Functionality in PCM or GCI
Highway Mode
Pin Name
PCM Mode
GCI Mode
Sub-frame
SDI_THRU SPI Data Through-
Selector, bit 2
put pin for Daisy
Chaining Operation
(Connects to the SDI
pin of the subse-
quent device in the
daisy chain)
SCLK
SDI
SDO
CS
SPI Clock Input
PCM/GCI Mode
Selector
3. Configuring the Si3050DC-EVB
The Si3050DC-EVB has six jumpers. The first five
control the boot-strap options for configuring the
Si3050. The default state is set to allow the Si3050 to be
controlled using the SPI bus. See Figure 1.
SPI Serial Data Input B1/B2 Channel
Selector
SPI Serial Data Out- Sub-frame
put
Selector, bit 1
SPI Chip Select
PCM Frame Sync
Input
PCM Input Clock
PCM Data Transmit
PCM Data Receive
Sub-frame
Selector, bit 0
GCI Frame Sync
Input
GCI Input Clock
GCI Data Transmit
GCI Data Receive
0 SDI_THRU 1
0
CS
1
0 SCLK 1
0 SDO 1
0
SDI
1
FSYNC
PCLK
DTX
DRX
Figure 1. SPI Control Mode Default State
Note:
This table denotes pin functionality after the rising
edge of RESET and mode selection.
Rev. 1.1
3
Si3050-EVB
Table 3. GCI Mode Sub-Frame Selection
SDI_THRU
GCI Subframe 0 Selected
(Voice channels 1–2)
GCI Subframe 1 Selected
(Voice channels 3–4)
GCI Subframe 2 Selected
(Voice channels 5–6)
GCI Subframe 3 Selected
(Voice channels 7–8)
GCI Subframe 4 Selected
(Voice channels 9–10)
GCI Subframe 5 Selected
(Voice channels 11–12)
GCI Subframe 6 Selected
(Voice channels 13–14)
GCI Subframe 7 Selected
(Voice channels 15–16)
1
1
1
1
0
0
0
0
SDO
1
1
0
0
1
1
0
0
CS
1
0
1
0
1
0
1
0
4
Rev. 1.1
Si3050-EVB
4. Evaluation Software
The Si3050 evaluation boards include an easy-to-use
graphical interface for controlling the evaluation
platform. This software allows the system designer to
characterize the Si3050 DAA performance without
constructing any custom hardware. The evaluation
software includes the following features:
5. Using the Si3050PPT-EVB
Application Software
A shortcut for starting the application software that
controls the evaluation board is installed in the Windows
Start Menu under the Programs folder in the “Si3050
Evaluation Software” folder.
Ability to read and write DAA registers using the SPI
or GCI bus
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either the time or
frequency domain using either PCM or GCI bus
Daisy-chain support
Transmit and receive path attenuation and gain
settings
Ring detection
Loop current measurement
5.1. Application Menus
Three pulldown menus are used to configure the
operation of the software:
Run:
Exit:
Stops the program
Save: Stores the audio waveform into .wav files
Configure:
DAA: Display hardware status and user
configuration. User can set advanced software options.
Reset DAA: Resets DAA and executes basic
initialization sequences on Reg 1, Reg 5–7, Reg 33–37,
and Reg 42
Configure
4.1. PC System Requirements
The application software for the Si3050 evaluation
boards has the following system requirements:
Windows98
®
, Windows2000
®
, or WindowsXP
®
Available parallel port
EPP
EPP
Design Tool
Map: Displays Register Map of Si3050
Signal Flow Diagram: Displays Signal Flow Diagram of
Si3050 and Si3019.
Transhybrid Loss Calculation: Calculate transhybrid loss
over frequency
Ringing: Help user program ring validation registers.
Register
or ECP parallel port mode for Windows 98
®
parallel port mode for Windows 2000
®
and
WindowsXP
®
Help:
Displays information about the evaluation
board
450 MHz Pentium II
®
or greater recommended
64 MB of memory or greater recommended
4.2. Installation
The supplied CD contains the Si3050PPT-EVB windows
driver files as well as a setup utility for installing the
evaluation software.
To install the Si3050PPT-EVB software, run the
installation program on the “Silicon Laboratories
Wireline Software CD.” The path for the installation
program is Si3050 Evaluation Software\setup.exe. The
installer guides the user through the installation process
for Si3050PPT-EVB.exe and the LabVIEW Run-Time
engine.
Rev. 1.1
5
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