Si826x
5
K
V LED E
MULATOR
I
NPUT
, 4.0 A I
SOLATED
G
ATE
D
RIVERS
Features
Pin-compatible, drop-in upgrades for
popular high speed opto-coupled
gate drivers
Low power diode emulator simplifies
design-in process
0.6 and 4.0 Amp peak output drive
current
Rail-to-rail output voltage
Performance and reliability
advantages vs. opto-drivers
Resistant to temperature and age
10x lower FIT rate for longer
service life
14x tighter part-to-part matching
Higher common-mode transient
immunity: >50 kV/µs typical
Robust protection features
Multiple UVLO ordering options
(5, 8, and 12 V) with hysteresis
60 ns propagation delay,
independent of input drive current
Wide V
DD
range: 5 to 30 V
3.75 and 5 kV reinforced isolation
UL, CSA, VDE
AEC-Q100 qualified
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
LGA8
Pin Assignments:
See page 24
1
UVLO
8
VDD
ANODE
2
e
7
VO
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8, LGA8
Industry Standard Pinout
ANODE 1
6
UVLO
VDD
Applications
IGBT/ MOSFET gate drives
Industrial, HEV and renewable
energy inverters
AC, Brushless and DC motor
controls and drives
Variable speed motor control in
consumer white goods
Isolated switch mode and UPS
power supplies
NC 2
e
5
VO
CATHODE 3
4
GND
SDIP6
Industry Standard Pinout
Safety Regulatory Approvals (Pending)
UL 1577 recognized
VDE certification conformity
Up to 5000 Vrms for 1 minute
IEC60747-5-2/VDE0884 Part 10
(basic/reinforced insulation)
CSA component notice 5A approval
CQC certification approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
GB4943.1
Patent pending
Description
The Si826x isolators are pin-compatible, drop-in upgrades for popular opto-
coupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL-
3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving
power MOSFETs and IGBTs used in a wide variety of inverter and motor control
applications. The Si826x isolated gate drivers utilize Silicon Laboratories'
proprietary silicon isolation technology, supporting up to 5.0 kV
RMS
withstand
voltage per UL1577. This technology enables higher-performance, reduced
variation with temperature and age, tighter part-to-part matching, and superior
common-mode rejection compared to opto-coupled gate drivers. While the input
circuit mimics the characteristics of an LED, less drive current is required,
resulting in higher efficiency. Propagation delay time is independent of input drive
current, resulting in consistently short propagation times, tighter unit-to-unit
variation, and greater input circuit design flexibility. As a result, the Si826x series
offers longer service life and dramatically higher reliability compared to opto-
coupled gate drivers.
Preliminary Rev. 0.9 4/13
Copyright © 2013 by Silicon Laboratories
Si826x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si826x
Functional Block Diagram
Diode
Emulator
VDD
A1
XMIT
I
F
REC
Output Driver
OUT
C1
GND
Diode Emulator Model and I-V Curve
3.0
2.5
10
V [V]
2.0
Anode
2.2 V
700
Cathode
1.5
1.0
0.5
0.0
0
5
10
15
I [mA]
20
25
30
2
Preliminary Rev. 0.9
Si826x
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Parametric Differences between Si826x and HCPL-0302 and HCPL-3120
Opto Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Pin Descriptions (SOIC-8, DIP8, LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
17.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
17.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
17.7. Si826x Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17.8. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Preliminary Rev. 0.9
3
Si826x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Input Current
Operating Temperature (Ambient)
Symbol
V
DD
I
F(ON)
T
A
Min
5
6
–40
Typ
—
—
—
Max
30
30
125
Unit
V
mA
°C
Table 2. Electrical Characteristics
1
V
DD
= 15 V or 30 V, GND = 0 V, I
F
= 6 mA, T
A
= –40 to +125 °C; typical specs at 25 °C
Parameter
DC Parameters
Supply Voltage
2
Supply Current (Output High)
Symbol
Test Conditions
Min
Typ
Max
Units
V
DD
I
DD
(V
DD
– GND)
I
F
= 10 mA
V
DD
= 15 V
V
DD
= 30 V
V
F
= –0.3 to +1.5 V
V
DD
= 15 V
V
DD
= 30 V
5
—
—
—
—
6
—
—
1.8
2.0
1.5
1.7
—
0.34
—
—
30
2.4
2.7
2.1
2.4
—
—
1
2.8
V
mA
mA
mA
mA
mA
mA
V
V
Supply Current (Output Low)
Input Current Threshold
Input Current Hysteresis
Input Forward Voltage (OFF)
Input Forward Voltage (ON)
Input Capacitance
I
DD
I
F(TH)
I
HYS
V
F(OFF)
V
F(ON)
C
I
Measured at ANODE with
respect to CATHODE.
Measured at ANODE with
respect to CATHODE.
f = 100 kHz,
V
F
= 0 V,
V
F
= 2 V
Si826xAxx devices
—
1.6
—
—
—
—
—
—
15
15
15
2.6
5.0
0.8
—
—
—
5.1
—
2.0
pF
Output Resistance High
(Source)
3
Output Resistance Low (Sink)
3
R
OH
Si826xBxx devices (I
OH
= -1 A)
Si826xAxx devices
R
OL
Si826xBxx devices (I
OL
= 2 A)
Notes:
1.
See "8.Ordering Guide" on page 25 for more information.
2.
Minimum value of (V
DD
- GND) decoupling capacitor is 1
µ
F.
3.
Both V
O
pins are required to be shorted together for 4.0 A compliance.
4.
When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
4
Preliminary Rev. 0.9
Si826x
Table 2. Electrical Characteristics (Continued)
1
V
DD
= 15 V or 30 V, GND = 0 V, I
F
= 6 mA, T
A
= –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Conditions
Si826xAxx devices (I
F
= 0),
(t
PW_IOH
< 250 ns)
(see Figure 2)
Min
—
Typ
0.4
Max
—
Units
Output High Current (Source)
3,4
I
OH
Si826xBxx devices (I
F
= 0),
(t
PW_IOH
< 250 ns),
(V
DD
– V
O
= 4 V)
(see Figure 2)
Si826xAxx devices
(I
F
= 10 mA),
(t
PW_IOL
< 250 ns)
(see Figure 1)
A
0.5
1.8
—
—
0.6
—
Output Low Current (Sink)
3,4
I
OL
Si826xBxx devices
(I
F
= 10 mA),
(t
PW_IOL
< 250 ns),
(V
O
- GND = 2.5 V)
(see Figure 1)
Si826xAxx devices
(I
OUT
= –100 mA)
A
1.2
4.0
—
—
V
DD
–
0.5
—
V
DD
–
0.4
V
DD
–
0.25
V
DD
—
—
High-Level Output Voltage
V
OH
Si826xBxx devices
(I
OUT
= –100 mA)
Si826xBxx devices
(I
OUT
= 0 mA),
(I
F
= 0 mA)
Si826xAxx devices
(I
OUT
= 100 mA),
(I
F
= 10 mA)
Si826xBxx devices
(I
OUT
= 100 mA),
(I
F
= 10 mA)
See Figure 10 on page 17.
V
DD
rising
See Figure 10 on page 17.
V
DD
falling
V
—
—
320
—
mV
Low-Level Output Voltage
V
OL
—
5
4.7
—
80
5.6
5.3
300
200
6.3
6.0
—
V
V
mV
UVLO Threshold +
(Si826xxAx mode)
UVLO Threshold –
(Si826xxAx mode)
UVLO lockout hysteresis
(Si826xxAx mode)
VDD
UV+
VDD
UV–
VDD
HYS
Notes:
1.
See "8.Ordering Guide" on page 25 for more information.
2.
Minimum value of (V
DD
- GND) decoupling capacitor is 1
µ
F.
3.
Both V
O
pins are required to be shorted together for 4.0 A compliance.
4.
When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
Preliminary Rev. 0.9
5
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