®
HIP1011D, HIP1011E
Data Sheet
November 18, 2004
FN4725.5
Dual Slot PCI Hot Plug Controllers
The HIP1011D, HIP1011E are the first ICs available for
independent control of two PCI Hot-Plug slots. The
HIP1011D has all the features and functionality of two single
PCI Hot-Plug slot controllers such as the HIP1011A but in
the same foot print area. Like the single slot HIP1011B, the
HIP1011E does not monitor output voltage nor respond to
undervoltage conditions.
The HIP1011D, HIP1011E are designed to be physically
placed in close proximity to two adjacent PCI slots thus
reducing layout complexity and placement costs in
assembly. The HIP1011D, HIP1011E provides independent
power control to each slot and the addition of discrete power
MOSFETs and a few passive components creates two
complete power control solutions. The IC integrates the
+12V and -12V current sensing switches for each slot.
Overcurrent (OC) protection is provided by sensing the
voltage across external current-sense resistors. In addition,
on-chip references are used to monitor the +5V, +3.3V and
+12V outputs for undervoltage (UV) conditions *. The two
PWRON inputs control the state of the switches, one each
for slot A and slot B outputs. During an OC condition on any
output, or a UV condition on the +5V, +3.3V or +12V outputs
*, a LOW (0V) is asserted on the associated FLTN output
and all associated switches are latched-off. The outputs
servicing the adjacent slot are unaffected.
The time to FLTN signal going LOW and MOSFET latch off
is user determined by a single capacitor from each FLTN pin
to ground. This added feature enables the HIP1011D,
HIP1011E to ignore system noise transients. The FLTN latch
is cleared when the PWRON input is toggled low again.
During initial power-up of the main VCC supply (+12V), the
PWRON input is inhibited from turning on the switches, and
the latch is held in the Reset state until the VCC input is
greater than 10V.
User programmability of the overcurrent threshold and turn-
on slew rate is provided. A resistor connected to the OCSET
pin programs the overcurrent threshold for both slots.
Capacitors connected to the gate pins set the turn-on rate.
* UV references do not apply to HIP1011E.
Features
• Independent Power Control of 2 PCI Slots
• Turn-Off Delay Time Adjustability
• Internal MOSFET Switches for +12V and -12V Outputs
•
µP
Interface for On/Off Control and Fault Reporting
• Adjustable Overcurrent Protection for All Eight Supplies
• Provides Fault Isolation
• Adjustable Turn-On Slew Rate
• Minimum Parts Count Solution
• No Charge Pump
• 100ns Response Time to Overcurrent
• Pb-Free Available (RoHS Compliant)
Applications
• PCI Hot-Plug
Ordering Information
PART NUMBER
HIP1011DCA*
HIP1011DCAZA*
(See Note)
HIP1011ECA*
HIP1011ECAZA*
(See Note)
TEMP.
RANGE (°C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
28 Ld SSOP
28 Ld SSOP
(Pb-free)
28 Ld SSOP
28 Ld SSOP
(Pb-free)
PKG.
DWG. #
M28.15
M28.15
M28.15
M28.15
* Add “-T” suffix for tape and reel option.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
Pinout
HIP1011D, HIP1011E (SSOP)
TOP VIEW
M12VO_2 1
M12VG_2 2
PWRON_2 3
FLTN_2 4
VSS 5
12VG_2 6
12VO_2 7
12VO_1 8
12VG_1 9
OCSET 10
FLTN_1 11
PWRON_1 12
M12VG_1 13
M12VO_1 14
28 M12VIN_2
27 3VISEN_2
26 3VS_2
25 5VISEN_2
24 5VS_2
23 3V5VG_2
22 12VIN_2
21 12VIN_1
20 3V5VG_1
19 5VS_1
18 5VISEN_1
17 3VS_1
16 3VISEN_1
15 M12VIN_1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP1011D, HIP1011E
Typical Application
12V
-12V
SLOT 1
5V
3.3V
C1
-12V BUS
M12VIN_1
M12G_1
M12VO_1
M12VIN_2
M12G_2
M12VO_2
12VIN_1
12VG_1
12VO_1
12VIN_2
12VG_2
12VO_2
PWRON_1
PWRON_2
OCSET
VSS
FLTN_1
OPT.
5VISEN_1
R1
5VS_1
3V5VG_1
3V5VG_2
5VS_2
5VISEN_2
3VISEN_1
R3
3VS_1
Q3
Q4
3VS_2
R4
3VISEN_2
FLTN_2
OPT.
C5
C6
3.3V BUS
5V
HIP1011D, HIP1011E
Q2
R2
Q1
C2
C3
+12V BUS
C4
FROM
SYSTEM CONTROLLER
R5
TO SYSTEM CONTROLLER
-12V
12V
SLOT 2
3.3V
FIGURE 1.
2
FN4725.5
November 18, 2004
5V BUS
HIP1011D, HIP1011E
Simplified Schematic (1/2 HIP1011D, HIP1011E)
5V
REF
SET (LOW = FAULT)
FAULT LATCH
LOW = FAULT
COMP
FLTN
-
+ 4.6V
INHIBIT
RESET
COMP
-
+ 2.9V
INHIBIT
COMP
TIED HIGH IN HIP1011D
TIED LOW IN HIP1011E
12V
IN
12V
IN
COMP
+
-
+
-
5V
S
12V
IN
3V5V
G
5V
REF
5V
ISEN
-
+ 10.6V
INHIBIT
12V
IN
5V ZENER
REFERENCE
COMP
LOW WHEN 12V
IN
< 10V
+
12V
IN
12V
IN
POWER-ON
RESET
-
+
-
3V
S
3V
ISEN
12V
IN
COMP
100µA
V
OCSET
OCSET
HIGH = FAULT
12V
IN
HIGH = SWITCHES ON
PWRON
COMP
GND
FIGURE 2.
3
+
-
+
+
12V
IN
-
-
M12V
IN
-
+
12V
IN
0.3Ω
12V
G
12V
O
M12V
IN
0.7Ω
M12V
G
M12V
O
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Pin Descriptions
PIN NO.
15, 28
4, 11
20, 23
DESIGNATOR
M12VIN
FLTN
3V5VG
FUNCTION
-12V Input
Fault Output
3.3V/5V Gate Output
DESCRIPTION
-12V Supply Input. Also provides power to the -12V overcurrent circuitry.
5V CMOS Fault Output; LOW = FAULT. An optional capacitor may be placed from this pin
to ground to provide additional immunity from power supply glitches.
Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the
startup ramp. During turn on, this capacitor is charged with a 25µA current source.
HIP1011D UV comparator disabled when this pin is below 9.6V nominal.
12V supply input for IC and 12VO. Both 12VIns to be connected to a single +12V supply.
Connect to the load side of the current sense resistor in series with source of external 3.3V
MOSFET.
Connect to source of 3.3V MOSFET. This connection along with (3VISEN) senses the
voltage drop across the sense resistor.
Connect to source of 5V MOSFET switch. This connection along with (5VISEN) senses the
voltage drop across the sense resistor.
Connect to the load side of the current sense resistor in series with source of external 5V
MOSFET.
Controls all four switches. High to turn switches ON, Low to turn them OFF.
21, 22
16, 27
17, 26
19, 24
18, 25
3, 12
6, 9
12VIN
3VISEN
3VS
5VS
5VISEN
PWRON
12VG
12V Input
3.3V Current Sense
3.3V Source
5V Source
5V Current Sense
Power On Control
Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the startup ramp for the +12V supply.
This capacitor is charged with a 25µA current source during startup.
HIP1011D UV comparator disabled when this pin >1.4V nominal.
Switched 12V Output
Switched 12V output. Rated for 0.5A.
7, 8
2, 13
1, 14
10
12VO
M12VG
M12VO
OCSET
Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the startup ramp for the M12V
supply. This capacitor is charged with 25µA during startup.
Switched -12V Output
Overcurrent Set
Switched -12V Output. Rated for 0.1A.
Connect a resistor from this pin to ground to set the overcurrent trip point of all eight
switches. All eight overcurrent trips can be programmed by changing the value of this
resistor. The default (6.04kΩ, 1%) is compatible with the maximum allowable currents as
outlined in the PCI specification.
Connect to common of power supplies.
5
VSS
Ground
4
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Absolute Maximum Ratings
12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . -0.5V to 12VIN+0.5V
M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V
M12VO, M12VG. . . . . . . . . . . . . . . . . . . . . . V
M12VIN
-0.5V to +0.5V
3VISEN, 5VISEN . . . . . . . . . . -0.5V to the Lesser of 12VIN or +7.0V
Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2KeV (HBM)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
Operating Conditions
12VIN Supply Voltage Range . . . . . . . . . . . . . . . . +10.8V to +13.2V
5V and 3.3V Input Supply Tolerances.
. . . . . . . . . . . . . . . . . . . . . ±10%
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1A
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
5V/3.3V SUPPLY CONTROL
5V Overcurrent Threshold
5V Overcurrent Threshold Voltage
5V Overcurrent Threshold Voltage
5V Undervoltage Trip Threshold
Nominal 5.0V and 3.3V Input Supply Voltages,
12V
IN
= 12V, M12V
IN
= -12V, T
A
= T
J
= 0 to 70°C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
OC5V
V
OC5V_1
V
OC5V_2
V
5VUV
t
5VUV
t
ON5V
I
OC3V
V
OC3V_1
V
OC3V_2
V
3VUV
t
3VUV
See Figure 24, Typical Application
V
OCSET
= 0.6V
V
OCSET
= 1.2V
(HIP1011D only)
(HIP1011D only)
C
3V5VG
= 0.022µF, C
5VOUT
= 2000µF, R
L
= 1Ω
See Figure 24, Typical Application
V
OCSET
= 0.6V
V
OCSET
= 1.2V
(HIP1011D Only)
(HIP1011D Only)
-
33
70
4.42
-
-
-
41
89
2.74
-
-
-
11.5
19
-
-
8
42
80
4.65
110
6.5
10
52
98
2.86
110
9.6
6.5
11.8
25.0
280
2
-
50
90
4.8
160
-
-
62
108
2.98
160
-
-
-
29
-
-
A
mV
mV
V
ns
ms
A
mV
mV
V
ns
V
ms
V
µA
µs
µs
5V Undervoltage Fault Response Time
5V Turn-On Time
(PWRON High to 5VOUT = 4.75V)
3V Overcurrent Threshold
3V Overcurrent Threshold Voltage
3V Overcurrent Threshold Voltage
3V Undervoltage Trip Threshold
3V Undervoltage Fault Response Time
3V5VG Undervoltage Enable Threshold
Voltage
3V Turn-On Time
(PWRON High to 3V
OUT
= 3.00V)
3V5VG V
OUT
High
Gate Output Charge Current
Gate Turn-On Time
(PWRON High to 3V5VG = 11V)
Gate Turn-Off Time
V
3V5VGENVth
(HIP1011D Only)
t
ON3V
C
3V5VG
= 0.022µF, C
3VOUT
= 2000µF,
R
L
= 0.43Ω
Vout_hi_35VG PWRON = High, FLTN = High
IC
3V5VG
t
ON3V5V
t
OFF3V5V
PWRON = High, V
3V+5VG
= 4V
C
3V5VG
= 0.033µF, 3V5VG Rising 10% to 90%
C
3V5VG
= 0.033µF, 3V5VG Falling 90% to 10%
5
FN4725.5
November 18, 2004
51单片机
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