Si 5 3 1 5 - EV B
S
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5315-EVB U
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Description
The Si5315 Evaluation Board User’s Guide provides for
a complete and simple evaluation of the functions,
features, and performance of the Si5315-EVB.
The Si5315 Synchronous Ethernet/Telecom jitter
attenuating clock multiplier has a comprehensive
feature set, including any-rate frequency synthesis,
multiple clock inputs, multiple clock outputs, alarm and
status outputs, hitless switching between input clocks,
and programmable output clock signal format (LVPECL,
LVDS, CML, CMOS). For more details, consult the
Silicon
Labs
timing
products
website
at:
www.silabs.com/timing.
TheSi5315-EVB has two differential clock input and
output ports that are AC terminated to 50 ohms and
then AC coupled to the Si5315. The XA-XB reference is
usually a 40 MHz crystal; however, there are provisions
for an external XA-XB reference clock (either differential
or single ended).
The evaluation board (EVB) can be powered using two
different approaches: external power supplies or by
USB. Jumper plugs are provided to select between
these two options. Jumper plugs are used to strap the
device pins for the various pin value options. Status
outputs are available on a ribbon connector header.
SMA connectors are used for the clock input, output,
and XA-XB reference signals.
Features
The Si5315-EVB includes the following:
Evaluation board
CD with the Si5315 documentation and the Si5315-
EVB User’s Guide
Function Block Diagram
Ext RefClk
Input
SMAs
Terminate
CKOUT1
Output
SMAs
Si5315
CKOUT2
USB
+3.3V
Vreg
LEDs
+3.3V
DUT PWR
1.8V to 3.3V
LED power
To DUT
Jumper
Headers
Control signals
status signals
Rev. 0.2 6/09
Copyright © 2009 by Silicon Laboratories
Si5315-EVB
Si5315-EVB
1. Introduction
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH
(T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two
equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon
Laboratories' 3rd-generation DSPLL
®
technology, which provides any-rate frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter
components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the
application level.
Refer to the Si5315 data sheet for technical details of the device.
Front
Figure 1. Si5315 EVB
Back
2
Preliminary Rev. 0.2
Si5315-EVB
2. Si53315-EVB Input and Output Clocks
Refer to the schematics, diagrams, and tables while reading this section.
2.1. Input Clocks
The Si5315 has two differential clock inputs that are AC terminated and AC coupled before being presented to the
Si5315. If the input clock frequencies are low (below 1 MHz), there are extra considerations that should be taken
into account. The Si5315 has a maximum clock input rise time specification of 11 ns that must be met (see CKNtrf
in the Si5315 data sheet). Also, if the input clock is LVCMOS, it might be advantageous to replace the input
coupling capacitors (C7, C12, C16, and C18) with zero ohm resistors. Regardless of the input format, if the clock
inputs are not roughly 50% duty cycle, it is highly recommended to avoid AC coupling. For input clocks that are far
off of 50% duty cycle, the average value of the signal that passes through the coupling capacitor will be significantly
off of the midpoint between the maximum and minimum value of the clock signal, resulting in a mismatch with the
common mode input threshold voltage (see V
ICM
in Table 2 of the Si5315 data sheet).
2.2. XA-XB Reference
To achieve very low jitter generation and for stability during holdover, the Si5315 requires a stable, low jitter
reference at its XA-XB pins. To that end, the EVB is configured with a 40 MHz fundamental mode crystal connected
between pins 6 and 7 of the Si5315. However, the Si5315-EVB is capable of using an external XA-XB reference
oscillator, either differential or single ended. J1 and J2 are the SMA connectors with AC termination. AC coupling is
also provided that needs to be installed at C6 and C8. Table 1 explains the changes of components that are
needed to implement an external XA-XB reference oscillator.
Table 1. XA-XB Reference Mode of Operation
Mode
Xtal
Ext Ref In+
Ext Ref In-
C6, C8
R8
XTAL/CLOCK
(J12 jumper, see Table 3.)
Notes:
1.
Xtal is 40 MHz.
2.
NC – no connect.
3.
NOPOP – do not install.
Ext Ref
J1
J2
install
NOPOP
M
NC
NC
NOPOP
install
L
2.3. Output Clocks
The clock outputs are AC coupled and are available on SMA's J5, J7, J9, and J11. For LVCMOS outputs, it might
be desirable to replace the AC coupling capacitors (C9, C14, C17, and C 20) with zero ohm resistors. Also, if
greater drive strength is desired for LVCMOS outputs, R6 and R10 can be installed.
Preliminary Rev. 0.2
3
Si5315-EVB
2.4. Pin Configuration
J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the
pins of the Si5315. Each pin can be strapped to be either H, M or L. H is achieved by installing a jumper plug
between the appropriate middle row pin and its VDD row pin. L is achieved by installing a jumper plug between the
appropriate middle row pin and its GND row pin. M is achieved by not installing a jumper plug.
2.5. Evaluation Board Power Options
The EVB can be powered from two possible sources: USB or external supplies. A 3.3 V supply is required to run
the LEDs because of their large forward drop. The Si5315 power supply can be separated from the 3.3 V supply so
that the Si5315 can be evaluated at voltages other than 3.3 V. It is important to note that when the USB supply is
being used, the EVB uses the USB port only for power and that the resulting power supply is strictly 3.3 V.
Here are the instructions for the various possibilities:
2.5.1. Two External Power Supplies
1. Install a jumper between J16.1 and J16.2 (labeled EXT).
2. No USB connection.
3. If the Si5315 is not being operated at 3.3 V, two different supplies should be connected to J14. Connect the
3.3 V supply to J14.1 and J14.2 (labeled 3.3 V and GND). Connect the SI5315 power supply between J14.2
and J14.3 (labeled GND and DUT).
4. If the Si5315 is to be operated at 3.3 V, J15 (labeled ONE PWR) can be installed, requiring only one external
supply. Connect 3.3 V power between J14.2 and J14.3 (labeled GND and DUT).
2.5.2. USB Power
1. With a USB cable, plug the EVB into a powered USB port.
2. Install a jumper between J16.2 and J16.3 (labeled USB).
3. Install a jumper at J15 (labeled ONE PWR).
2.5.3. USB 3.3 V Power, External Si5315 Power
1. Install a jumper between J16.2 and J16.3 (labeled USB).
2. No jumper at J15 (labeled ONE PWR).
3. Connect the Si5315 power supply between J14.2 and J14.3 (labeled GND and DUT).
4
Preliminary Rev. 0.2
Si5315-EVB
3. Connectors and LEDs
3.1. LEDs
Table 2. LED Descriptions
LED
D1
D2
D3
D4
D5
D6
Color
Yellow
Red
Red
Red
Green
Green
Label
CS_CA
LOS2
LOS1
LOL
DUT_PWR
3.3V
Significance
ON = clock input 2 selected, else clock 1
ON = no valid clock input 2
ON = no valid clock input 1
ON = Si5315 is not locked
ON = Si5315 power is present
ON = 3.3V power is present
3.2. Connectors, Headers, and Jumpers
Refer to Figure 2 to locate the items described in this section.
C7, C12, C16, C18
J12
R8
U1,
Si5315
J16
J13
J15
Figure 2. Connectors, Headers, and Jumper Locations
Preliminary Rev. 0.2
5
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