CDB4334/8/9
Evaluation Board for CS4334/8/9 Family of Products
Features
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Demonstrates
Description
The CDB4334/8/9 evaluation board is an excellent
means for quickly evaluating the CS4334/8/9 family of
24-bit, stereo D/A converters. Evaluation requires an an-
alog signal analyzer, a digital signal source and a power
supply. Analog outputs are provided via RCA connectors
for both channels.
The CS8414 digital audio receiver I.C. provides the sys-
tem timing necessary to operate the Digital-to-Analog
converters and will accept AES/EBU, S/PDIF, and EIAJ-
340 compatible audio data. The evaluation board may
also be configured to accept external timing signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4334, CDB4338, CDB4339
recommended layout and
grounding arrangements
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CS8414 Receives AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
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Digital and Analog Patch Areas
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Requires only a digital signal source and
power supplies for a complete Digital-to-
Analog-Converter system
I/O for
Clocks
and Data
CS8414
Digital
Audio
Interface
CS4334/38/39
Analog
Filter
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 1998
(All Rights Reserved)
AUG ‘98
DS248DB2
23
CDB4334/8/9
CDB4334/8/9 SYSTEM OVERVIEW
The CDB4334/8/9 evaluation board is an excellent
means of quickly evaluating the CS4334/8/9. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources in-
cluding the majority of digital audio test equip-
ment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB4334/8/9 schematic has been partitioned
into 7 schematics shown in Figures 2 through 8.
Each partitioned schematic is represented in the
system diagram shown in Figure 1. Notice that the
the system diagram also includes the interconnec-
tions between the partitioned schematics.
The CS8414 does not support a compatible data
format for the CS4335, CS4336 or CS4337. As a
result, an evaluation board is not available for these
devices. However, the evaluation board does allow
external generation of clocks and data, bypassing
the CS8414, and will support the CS4335/36/37 in
this configuration.
by the CSLR/FCK jumper. This allows the CS8414
to decode the de-emphasis bit from the digital au-
dio interface for control of the CS4334/8/9 de-em-
phasis filter.
When the Error Information Switch is activated,
the CS8414 operates in the Error and Frequency in-
formation mode. The information displayed by the
LED’s can be decoded by consulting the CS8414
data sheet. It is likely that the de-emphasis control
for the CS4334/8/9 will be erroneous and produce
an incorrect audio output if the Error Information
Switch is activated and the CS4334/8/9 is in the in-
ternal serial clock mode.
Encoded sample frequency information can be dis-
played provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin locat-
ed on the CS8414. When an LED is off, this indi-
cates a "0" on the corresponding pin. Neither the L
or R option of CSLR/FCK should be selected if the
FCK pin is being driven by a clock signal.
The evaluation board has been designed such that
the input can be either optical or coax, Figure 6.
However, both inputs can not be driven simulta-
neously.
CS4334/8/9 DIGITAL TO ANALOG
CONVERTER
A description of the CS4334/5/6/7/8/9 is included
in the CS4334/5/6/7/8/9 data sheet.
CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers
M0, M1, M2, and M3, as described the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4334/8/9, shown in
Figures 4-7 of the CS4334/8/9 datasheet. The de-
fault settings for M0-M3 on the evaluation board
are given in Tables 2-4. The compatible data for-
mats we have chosen for the CS8414 and
CS4334/8/9 are:
CS8414 format 2 ; CS4334
CS8414 format 5 ; CS4338
CS8414 format 6 ; CS4339
CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 in-
clude a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs mas-
ter clock. The operation of the CS8414 and a dis-
cussion of the digital audio interface are included in
the CS8414 Datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED’s display
channel status information for the channel selected
24
DS248DB2
CDB4334/8/9
ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters and a pair of 3-pole active filters.
The passive filters are provided as an example for
cost-sensitive desigins. The active filters demon-
strate a higher performance alternative with better
out-of-band noise rejection. The passive filters,
Fig. 4, have a corner frequency of approximately
95 kHz with JP3 and JP6 installed and 190 kHz
without JP3 and JP6. The 3-pole active filters are
shown in Fig. 3. The output filter options are se-
lected via the Left and Right Channel filter jump-
ers, Fig. 2.
an I/O buffer where jumpers HDR1-HDR6 deter-
mine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a re-
ceiver with jumpers HDR1-HDR6 in the EXTER-
NAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4334/8/9 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 9 shows CDB power arrange-
ments. The CDB4334/8/9 ground plane is divided
in a manner to control to digital return currents in
order to minimize noise. The decoupling capacitors
are located as close to the CS4334/8/9 as possible.
Extensive use of ground plane fill on both the ana-
log and digital sections of the evaluation board
yield large reductions in radiated noise effects.
INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 10. The 74HC243 transceiver functions as
DS248DB2
25
CDB4334/8/9
CONNECTOR
+5 V
GND
Digital input
Optical input
Digital I/O
AOUTLA
AOUTRA
AOUTLP
AOUTRP
INPUT/OUTPUT
input
input
input
input
input/output
output
output
output
output
+ 5 Volt power
SIGNAL PRESENT
ground connection from power supply
digital audio interface input via coax
digital audio interface input via optical
I/O for master, serial, left/right clocks and serial data
left channel analog output with 3-pole active filter
right channel analog output with 3-pole active filter
left channel analog output with single-pole passive filter
right channel analog output with single-pole passive filter
Table 1. System Connections
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
MCLK
Left Channel
Filter
Right Channel
Filter
PURPOSE
Selects channel for CS8414
channel status information
CS8414 mode selection
POSITION
HI
LO
*Low
*High
*Low
*Low
INT
*EXT
*8414
DEM
*8414
EXT
x1
÷2
Active
Passive
Active
Passive
FUNCTION SELECTED
See CS8414 Datasheet for details
See CS8414 Datasheet for details
Internal SCLK Mode
External SCLK Mode
CS8414 de-emphasis
De-emphasis input static high
Selects CS8414 as source
Digital I/O header becomes an source
Selects Base Rate Mode
Selects High Rate Mode
Selects 3-pole active filter
Selects Single-pole passive filter
Selects 3-pole active filter
Selects Single-pole passive filter
Selects SCLK Mode
Selects source of de-emphasis
control
Selects source of clocks and
audio data
Selects High-Rate or Base-Rate
Modes
Selects Active 3-pole or passive
single-pole filter
Selects Active 3-pole or passive
single-pole filter
*Default setting from factory
Notes:
The CS8414 data format requires the CS4334 to operate in the external serial clock mode.
Table 2. CDB4334 Jumper Selectable Options
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DS248DB2
CDB4334/8/9
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
MCLK
Left Channel
Filter
Right Channel
Filter
PURPOSE
Selects channel for CS8414
channel status information
CS8414 mode selection
POSITION
HI
LO
*High
*Low
*High
*Low
INT
*EXT
*8414
DEM
*8414
EXT
x1
÷2
Active
Passive
Active
Passive
FUNCTION SELECTED
See CS8414 Datasheet for details
See CS8414 Datasheet for details
Internal SCLK Mode
External SCLK Mode
CS8414 de-emphasis
De-emphasis input static high
Selects CS8414 as source
Digital I/O header becomes an source
Selects Base Rate Mode
Selects High Rate Mode
Selects 3-pole active filter
Selects Single-pole passive filter
Selects 3-pole active filter
Selects Single-pole passive filter
Selects SCLK Mode
Selects source of de-emphasis
control
Selects source of clocks and
audio data
Selects High-Rate or Base-Rate
Modes
Selects Active 3-pole or passive
single-pole filter
Selects Active 3-pole or passive
single-pole filter
*Default setting from factory
Notes:
The CS8414 data format requires the CS4338 to operate in the external serial clock mode.
Table 3. CDB4338 Jumper Selectable Options
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
MCLK
Left Channel
Filter
Right Channel
Filter
PURPOSE
Selects channel for CS8414
channel status information
CS8414 mode selection
POSITION
HI
LO
*Low
*High
*High
*Low
INT
*EXT
*8414
DEM
*8414
EXT
x1
÷2
Active
Passive
Active
Passive
FUNCTION SELECTED
See CS8414 Datasheet for details
See CS8414 Datasheet for details
Internal SCLK Mode
External SCLK Mode
CS8414 de-emphasis
De-emphasis input static high
Selects CS8414 as source
Digital I/O header becomes an source
Selects Base Rate Mode
Selects High Rate Mode
Selects 3-pole active filter
Selects Single-pole passive filter
Selects 3-pole active filter
Selects Single-pole passive filter
Selects SCLK Mode
Selects source of de-emphasis
control
Selects source of clocks and
audio data
Selects High-Rate or Base-Rate
Modes
Selects Active 3-pole or passive
single-pole filter
Selects Active 3-pole or passive
single-pole filter
*Default setting from factory
Table 4. CDB4339 Jumper Selectable Options
DS248DB2
27
FPGA/CPLD
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