MXED202
128-Channel OLED Row Driver
Preliminary
FEATURES:
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For all Passive-Matrix Organic Light Emitting
Diode (OLED) Displays
Monochome and Color
Small Molecule and Polymer
Common-Cathode Row Switching
CMOS High Voltage Process: 5V-30V
Display Panel Supply Compatible
128 Output Channels, Cascadable;
Configurable 120-Output Mode
150mA Maximum Current Capability per
Channel (two channels maximum active
simultaneously)
20 Ohm Maximum Row Switch “On”
Resistance
Token-Based Control; Bidirectional data
transfer; Single- and Dual-Token Modes
3V to 5.5V logic supply
up to 100 kHz Clock Frequency
Gold-Bumped Die @ ~60 micron Output Pitch
TCP package option
Compatible with
Clare Micronix
100 Series
OLED Column Drivers
OVERVIEW:
Clare Micronix’s MXED202 is a row-multiplexed
display driver for OLED panel displays. The
MXED202 directly supports up to 128-row OLED
panel displays, or can be cascaded for controlling
additional rows. The MXED202’s low “on” switch
resistance ensures uniform luminance at rapid row
scan rates. This is the first production row driver
for OLED display OEM’s, enabling the development
and production of this new standard in flat-panel
display technology.
FUNCTIONAL DESCRIPTION:
MXED102 or similar column driver, or a controller.
In “normal mode” (single token), the token may be
entered at either end of the MXED202 row shift
register (SRIN or SLIN), depending on the shift di-
rection selection control “Shift Right” (SHR). The
token bit is shifted one row (one channel) per clock
cycle (CLK), during which time only one row maxi-
Device settings, such as token direction, number mum is active at a time. In “dual mode” (DUAL),
of active rows, dual or single-token mode, and oth- the token bit is entered at one end and automati-
cally in the center, and again the token bits may be
ers, are set by dedicated input pins.
selectively shifted left or right at the CLK rate; dur-
Figure 1 is a block diagram of the MXED202. Each ing which time only two rows maximum are active
row output has two possible sources: ground, to at a time. The MXED202 may be used for either
turn the LED on, and VOH (Voltage Output High) to 128- or 120-row display panels. When the “Select
turn the LED off. To begin a scan of the rows, the 128” (S128) control input is low, the MXED202 is
user inputs a token bit so that it is high at the rising set for 120 outputs. When S128 is low, Rows 4
edge of CLK, which is typically provided by the through 123 must be used. (Note: A lesser num-
The MXED202 is capable of sinking current for up
to 128 rows (LED cathodes) of an OLED display.
One or two outputs may be active at a time. For
displays requiring more than 150mA sink current
per row, multiple MXED202’s may be placed in
parallel.
14180B
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November 12, 2002
Preliminary
FUNCTIONAL DESCRIPTION - CONTINUED
ber of rows may be used by resetting the MXED202
(RSTB) at any time, truncating the shift cycle.)
Please refer to the Table 1, Token Shift Options.
The MXED202 fully supports column precharge of
OLED display panels. During column precharge
the active row output will be high (VOH) from the
time CLK occurs until PCB (typically provided by
the column driver) goes high. When PCB goes high,
indicating that precharge is completed, the active
row output will go low, allowing the diode to turn on.
All inactive row outputs will remain high.
MXED202
The “off” output voltage, VOH, is connected to the
output of an internal op-amp. This op-amp may be
used to generate VOH, or it may be bypassed. If it
is bypassed, VOH is tied directly to VMAX, as are
inputs VDRV and INV. If the op-amp is to be used
to generate VOH, VDRV is used as the non-invert-
ing op-amp input, and INV is used as the inverting
op-amp input. External resistors are used to set
the gain, and thus VOH. Figure 4 shows the circuit
options for generating VOH.
FIGURE 1 - MXED202 BLOCK DIAGRAM
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14180B
Preliminary
MXED202
MXED202 DATA SHEET
Table of Contents
FEATURES .............................................................................................................. 1
OVERVIEW .............................................................................................................. 1
FUNCTIONAL DESCRIPTION ............................................................................. 1-2
FIGURE 1 - BLOCK DIAGRAM .................................................................................................................... 2
TABLE 1 - TOKEN SHIFT OPTIONS .......................................................................................................... 4
TABLE 2 - INPUT/OUTPUT PAD DESCRIPTIONS ................................................................................. 4-5
ELECTRICAL SPECIFICATIONS .............................................................................................................. 6-9
FIGURE 2 - TYPICAL ROW OUTPUT CHARACTERISTICS ..................................................................... 8
FIGURE 3 - TIMING DIAGRAMS .......................................................................................................... 10-11
FIGURE 4 - VOH GENERATION OPTIONS .............................................................................................. 12
MECHANICAL SPECIFICATIONS ........................................................................ 13
DIE SPECIFICATIONS ........................................................................................... 13
FIGURE 5 - DIMENSIONAL DRAWING ..................................................................................................... 14
BGA SPECIFICATIONS ......................................................................................... 18
ORDERING INFORMATION ...................................................................................................................... 20
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Preliminary
TABLE 1 - TOKEN SHIFT OPTIONS
D U AL
S 128
00
Token
0
1
123
127
01
Input
4
0
- SH R
10
Posi ti on
123,63
127,63
4,64
0,64
11
Outputs U sed
MXED202
120-Row Mode uses rows 4-123
(rows 0-3, 124-127 N/C )
128-Row Mode uses rows 0-127
INPUT/OUTPUT PAD DESCRIPTIONS
Name
RTN
I/O/A
I
I
I
D escri pti on
Return for all di splay current.
ground.
C onnect to a low i mpedance
GND
VC C
Ground, the negati ve return for all chi p current and the di gi tal logi c
"zero" reference level.
The logi c voltage posi ti ve supply. MXED 202 logi c operates
between VC C and VSS.
Thi s voltage maxi mum i s the hi ghest posi ti ve power supply
voltage present on the chi p. Inputs to the chi p should not exceed
VMAX to avoi d forward bi asi ng i nternal substrate di odes.
Row Voltage Output Hi gh supply. Thi s pi n i s normally connected
to an external power supply pi n VMAX wi th bypass capaci tor
(typi cally 4.7uF), and to pi n D RV. Alternati vely, an i nternal
ampli fi er can generate VOH from an i nput voltage D RV.
Inverti ng i nput to Voltage Regulator Op Amp, to whi ch an i nput
Resi stor RI and feedback Resi stor RF may be connected to
develop VOH from VD RV; see D RV pi n. See Fi gure 4.
When not connected to VOH and VMAX, a D ri ve Reference
Voltage >1V can be connected to the D RV pi n.
Acti ve hi gh stati c Shi ft Ri ght control i nput: When SHR=0, the token
bi t travels from R127 to R0, wi th SLIN bei ng the token i nput, SRIN
the token output. SHR should always be dri ven to the desi red
logi c level. C onfi gurati on pi n.
Shi ft Ri ght Input. Thi s bi -di recti onal pi n i s the token i nput when
SHR i s hi gh, and the token output (for synchroni zati on or
cascadi ng) when SHR i s low. When confi gured as an i nput, thi s
pi n should always be dri ven. Normally low, SRIN should be dri ven
hi gh once per frame to enter the token i nto the shi ft regi ster.
Shi ft Left Input. Thi s bi -di recti onal pi n i s the token i nput when
SHR i s low, and the token output (for synchroni zati on or
cascadi ng) when SHR i s hi gh. When confi gured as an i nput, thi s
pi n should always be dri ven. Normally low, SLIN should be dri ven
hi gh once per frame to enter the token i nto the shi ft regi ster.
VMAX
I
VOH
I/O/A
INV
D RV Note: If VD RV
<0.3V, all row ci rcui try
i s powered down.
I
I
SHR
I
SRIN
I/O
SLIN
I/O
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14180B
Preliminary
INPUT/OUTPUT PAD DESCRIPTIONS (continued)
MXED202
Name
DUAL
I/O/A Description
I
DUAL tokens are seeded into the first and middle shift register
cells from SRIN or SLIN when DUAL is static active high. When
low, a single token is active. Configuration pin.
The rising edge of the CLK input shifts the token along the internal
shift register to activate successive rows.
If the PreCharge Bar input is low on the rising edge of CLK, all
row outputs will be switched to VOH to enable display panel
precharging (via the column driver) until PCB returns high.
Holding PCB high disables column precharge.
This input must be tied to ground.
This input must be tied to ground.
Select 128 row driver output mode when static active high. When
low, 120 row driver output mode is selected. Configuration pin.
CLK
I
PCB
I
MONO
MOD
S128
I
I
I
ROPT
Resistor OPTion pin, normally N/C for digitally controlled
precharge timing (PCB), or when precharge is disabled. When a
resistor R is connected between ROPT and PCB, and a capacitor
I/O/A C is connected between PCB and VSS, the precharge time will
be RC/1.65 when measured from the rising edge of CLK to the
falling edge of ROPT. The timing components should be selected
such that RC/1.65 not exceed 10% of the row active time.
I
O
Reset Bar - active low reset input, clears all the shift register cells,
eliminating token content.
Row driver outputs. R(0)-R(127) are used in 128 output mode,
S128=1. Only R(4)-R(123) should be connected when S128=0.
High voltage REFerence is an internally generated PFET switch
drive voltage (approximately VOH-5V), which should be bypassed
to VOH with a 2200pF external capacitor.
Low voltage REFerence is an internally generated NFET switch
drive voltage (approximately GND+5V), which should be bypassed
to GND with a 2200pF external capacitor.
Leave Unconnected or tie to VMAX.
Leave Unconnected or tie to GND.
RSTB
R(n)
HREF
O
LREF
NRMH
NRML
O
O
O
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