Features
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Full Range of Matrices with up to 480K Gates
0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM and DPRAM Compilers
Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
3 and 5 Volts Operation; Single or Dual Supply Mode
High Speed Performances
– 420 ps Max NAND2 Propagation Delay at 4.5V, 670 ps at 2.7 and FO = 5
– Min 650 MHz Toggle Frequency at 4.5V and 340 MHz at 2.7V
Programmable PLL Available on Request
High System Frequency Skew Control through Clock Tree Synthesis Software
Low Power Consumption:
– 1.96 µW/Gate/MHz at 5V
– 0.6 µW/Gate/MHz at 3V
Integrated Power On Reset
Matrices With a Max of 484 Fully Programmable Pads
Standard 3, 6, 12 and 24 mA I/Os
Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 KV) and Latch-up Protected I/O
High Noise and EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery and Core
– Application Dependent Supply Routing and Several Independent Supply Sources
Wide Range of Hermetic and Plastic Packages
Delivery in Die Form with 94.6 µm Pad Pitch
Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
Cadence
®
, Mentor
™
, Vital and Synopsys
®
Reference Platforms
EDIF and VHDL Reference Formats
Available In Commercial, Industrial and Military Quality Grades (for Space Application
see MG2RT and MG2RTP Specifications)
QML Q with SMD 5962-00B02
350K Used Gates
0.5 µm CMOS
Sea of Gates
MG2
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Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 480K gates cover most system integration needs. The MG2 is manufactured using
a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2.
The base cell architecture of the MG2 series provides high routability of logic with
extremely dense compiled memories: RAM and DPRAM. ROM can be generated
using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customization dependent supply routing, noise filtering, skew controlled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
The MG2 is supported by an advanced software environment based on industry stan-
dards linking proprietary and commercial tools. Verilog, Modelsim, Design Compiler
are the reference front-end tools. Floor planning associated with timing driven layout
provides a short back-end cycle.
The MG2 library allows straight forward migration from MG1 Sea of Gates. A netlist
based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
4137O–AERO–06/05
Table 1.
List of Available MG2 Matrices
Type
MG2044
(1)
MG2091
(1)
MG2194
MG2265
(1)
MG2360
MG2480
Total Gates
44616
91464
193800
264375
361680
481143
Typical Usable
Gates
31200
64000
135600
185000
253100
336800
Total Pads
173
237
333
385
445
507
Maximum Programmable I/Os
150
214
310
362
422
484
Note:
1. Not available for new designs.
Libraries
The MG2 cell library has been designed to take full advantage of the features offered by both
logic and test synthesis tools.
Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST
methodologies.
More complex macro functions are available in VHDL, for example: I2C, UART,
Timer, etc.
Block Generators
Block generators are used to create a customer-specific simulation model and metallisation pat-
tern for regular functions like RAM and DPRAM. The basic cell architecture allows one bit per
cell for RAM and DPRAM. The main characteristics of these generators are summarized below.
Table 2.
Block Generator Capability
Maximum
Size (bits)
32k
32k
Typical Characteristics (16k bits) at 5V
Bits/Word
1-36
1-36
Access Time (ns)
8
8.6
Used Cells
20 k
23 k
Function
RAM
DPRAM
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MG2
4137O–AERO–06/05
MG2
I/O Buffer Interfacing
I/O Flexibility
Inputs
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level
translator is located close to each buffer.
Input buffers with CMOS or TTL thresholds are non-inverting and feature versions with and with-
out hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down
terminators. For special purposes, a buffer allowing direct input to the matrix core is available.
Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA
drive at 5V, low noise buffers with 12 mA drive at 5V.
Outputs
Clock Generation and PLL
Clock Generation
Atmel offers 6 different types of oscillators: 4 high frequency crystal oscillators and 2 RC oscilla-
tors. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10
ms.
Frequency (MHz)
Oscillators
Xtal 7M
Xtal 20M
Xtal 50M
Xtal 100M
RC 10M
RC 32M
Max 5V
12
28
70
130
10
32
Max 3V
7
17
40
75
10
32
Typical
5V
1.2
2.5
7
16
2
3
Consumption (mA)
3V
0.4
0.8
2
5
1
1.5
PLL
Contact factory.
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4137O–AERO–06/05
Power Supply
and Noise
Protection
The speed and density of the SCMOS3/2 technology causes large switching current spikes, for
example, when:
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16 high current output buffers switch simultaneously,
or 10% of the 480,000 gates are switching within a window of 1 ns.
Sharp edges and high currents cause some parasitic elements in the packaging to become sig-
nificant. In this frequency range, the package inductance and series resistance should be taken
into account. It is known that an inductor slows down the settling time of the current and causes
voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself
or disturb the external application (ground bounce).
In order to improve the noise immunity of the MG core matrix, several mechanisms have been
implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O
buffer switching noise and the other to protect the I/O buffers against the switching noise coming
from the matrix.
I/O Buffers
Switching
Protection
Three features are implemented to limit the noise generated by the switching current:
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The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal regulator.
A design rule concerning the number of buffers connected on the same power supply line
has been imposed.
Matrix Switching
This noise disturbance is caused by a large number of gates switching simultaneously. To allow
Current Protection
this without impacting the functionality of the circuit, three new features have been added:
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Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop.
A power supply network has been implemented in the matrix. This solution reduces the
number of parasitic elements such as inductance and resistance and constitutes an artificial
VDD and Ground plane. One mesh of the network supplies approximately 150 cells.
A low pass filter has been added between the matrix and the input to the output buffer. This
limits the transmission of the noise coming from the ground or the VDD supply of the matrix
to the external world via the output buffers.
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MG2
4137O–AERO–06/05
MG2
Packaging
Atmel offers a wide range of packaging options which are listed below:
Table 3.
Packaging Options
Pins
Package Type
(1)
CQPF
Min./Max
132
160
196
256
352
Lead Spacing
(mils)
25,6
25,6
25
20
20
MQFP
Notes:
1. Contact Atmel Local Design Centers to check the availability of the matrix/package
combination.
2. Contact factory.
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4137O–AERO–06/05
stm32/stm8
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