A29160 Series
2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Add
WP
to TSOP and TFBGA package
Modify the pin configuration error of TFBGA
Modify the error of CFI codes of VCC Max, VCC Min, and minor version
Update byte mode, word mode program time, sector and chip erase time;
typical word mode active read current chart
Add Part Numbering Scheme
Issue Date
July 13, 2009
November 30, 2009
April 7, 2010
Remark
Preliminary
0.3
Page 1: Change from typical 100,000 cycles to minimum 100,000 cycles
November 25, 2010
(November, 2010, Version 0.3)
AMIC Technology, Corp.
A29160 Series
2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
Single power supply operation
- Full voltage range: 4.5 to 5.5 volt for read and write
operations
Access times:
- 55/70 (max.)
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
-
0.5uA typical CMOS standby (
WP
= VCC or Float)
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors
-
8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Minimum 100,000 program/erase cycles per sector
20-year data retention at 125°C
-
Reliable operation for the life of the system
CFI (Common Flash Interface) compliant
- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Ready /
BUSY
pin (RY /
BY
)
- Provides a hardware method of detecting completion of
program or erase operations (not available on 44-pin
SOP)
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data
WP
input pin (48 pins TSOP, TFBGA)
- At V
IL
, protects the 16Kbyte boot sector from erasure
regardless of sector protect/unprotect status.
- At V
IH
, allows removal of boot sector protection.
Package options
-
44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
-
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A29160 is a 16Mbit, 5.0 volt-only Flash memory
organized as 2,097,152 bytes of 8 bits or 1,048,576 words of
16 bits each. The 8 bits of data appear on I/O
0
- I/O
7
; the 16
bits of data appear on I/O
0
~I/O
15
. The is offered in 48-ball
FBGA, 44-pin SOP and 48-Pin TSOP packages. This device
is designed to be programmed in-system with the standard
system 5.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29160 can also be programmed in standard EPROM
programmers.
The A29160 has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29160 has a second toggle bit, I/O
2
, to indicate whether the
addressed sector is being selected for erase. The A29160
also offers the ability to program in the Erase Suspend mode.
The standard A29160 offers access times of 55 and 70,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
chip enable (
CE
), write enable (
WE
) and output enable
(
OE
) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29160 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
(November, 2010, Version 0.3)
1
AMIC Technology, Corp.
A29160 Series
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY /
BY
pin, or by
reading the I/O
7
(
Data
Polling) and I/O
6
(toggle) status bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29160 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Write Protect (
WP
) features protects the 16 Kbyte boot
sector from erasure by asserting a logic low on the
WP
pin,
whether or not the sector had been previously protected.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data. The
RESET
pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers power-saving features. The system can
place the device into the standby mode. Power consumption
is greatly reduced in the standby modes.
Pin Configurations
SOP
RESET
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
I/O
0
I/O
8
I/O
1
I/O
9
I/O
2
I/O
10
I/O
3
I/O
11
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
WE
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
WP
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
TSOP (I)
10
11
12
13
14
15
16
17
18
19
20
21
22
A29160M
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A29160V
(November, 2010, Version 0.3)
2
AMIC Technology, Corp.
A29160 Series
Pin Configurations (continued)
(November, 2010, Version 0.3)
3
AMIC Technology, Corp.
A29160 Series
Block Diagram
RY/BY
VCC
VSS
I/O
0
- I/O
15
(A-1)
Sector Switches
Erase Voltage
Generator
State
Control
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
Input/Output
Buffers
RESET
WP
WE
BYTE
Command
Register
CE
OE
STB
VCC Detector
Timer
Y-Decoder
Y-Gating
Address Latch
A0-A19
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A19
I/O
0
- I/O
14
I/O
15
I/O
15
(A
-1
)
A
-1
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Write Protection
Output Enable
Hardware Reset
Selects Byte Mode or Word Mode
Ready/
BUSY
- Output
Ground
Power Supply
Pin not connected internally
CE
WE
WP
OE
RESET
BYTE
RY/
BY
VSS
VCC
NC
(November, 2010, Version 0.3)
4
AMIC Technology, Corp.
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